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参数资料
| 型号： | ISL6612BIRZ |
| 厂商： | Intersil |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 10-DFN |
| 标准包装： | 100 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 7 V ~ 13.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 管件 |
ISL6612B, ISL6613B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating
temperature range. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
Three-State Upper Gate Falling Threshold
VCC = 12V
2.60
V
Shutdown Holdoff Time
t TSSHD
-
245
-
ns
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 7)
LGATE Turn-On Propagation Delay (Note 7)
UGATE Turn-Off Propagation Delay (Note 7)
LGATE Turn-Off Propagation Delay (Note 7)
LG/UG Three-State Propagation Delay (Note 7)
t RU
t RL
t FU
t FL
t PDHU
t PDHL
t PDLU
t PDLL
t PDTS
V PVCC = 12V, 3nF Load, 10% to 90%
V PVCC = 12V, 3nF Load, 10% to 90%
V PVCC = 12V, 3nF Load, 90% to 10%
V PVCC = 12V, 3nF Load, 90% to 10%
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
-
-
-
-
-
-
-
-
-
26
18
18
12
10
10
10
10
10
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT (Note 7)
Upper Drive Source Current
I U_SOURCE
V PVCC = 12V, 3nF Load
-
1.25
-
Α
Upper Drive Source Impedance
R U_SOURCE 150mA Source Current
1.25
2.0
3.0
Ω
Upper Drive Sink Current
Upper Drive DC Sink Impedance
Lower Drive Source Current
I U_SINK
R U_SINK
I L_SOURCE
V PVCC = 12V, 3nF Load
150mA Source Current
V PVCC = 12V, 3nF Load
-
0.9
-
2
1.6
2
-
3.0
-
Α
Ω
A
Lower Drive Source Impedance
R L_SOURCE 150mA Source Current
0.85
1.35
2.2
Ω
Lower Drive Sink Current
Lower Drive Sink Impedance
I L_SINK
R L_SINK
V PVCC = 12V, 3nF Load
150mA Sink Current
-
0.60
3
0.80
-
1.35
A
Ω
NOTE:
7. Limits established by characterization and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
-
3
3, 8
4
N/C
PWM
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.
4
5
6
7
5
6
7
9
GND
LGATE
VCC
PVCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives in ISL6613B; only the lower gate drive in ISL6612B.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
6
FN9205.4
May 1, 2012
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