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参数资料
| 型号： | ISL6622CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR SYNC BUCK 8-SOIC |
| 标准包装： | 1 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 20ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 1241 (CN2011-ZH PDF) |
| 其它名称： | ISL6622CBZ-TDKR |
ISL6622
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested (Continued)
PARAMETER
Three-State Upper Gate Falling Threshold (Note 4)
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
SYMBOL
t RU
t RL
t FU
t FL
t PDHU
t PDHL
t PDLU
t PDLL
TEST CONDITIONS
VCC = 12V
V VCC = 12V, 3nF Load, 10% to 90%
V VCC = 12V, 3nF Load, 10% to 90%
V VCC = 12V, 3nF Load, 90% to 10%
V VCC = 12V, 3nF Load, 90% to 10%
V VCC = 12V, 3nF Load, Adaptive
V VCC = 12V, 3nF Load, Adaptive
V VCC = 12V, 3nF Load
V VCC = 12V, 3nF Load
MIN
-
-
-
-
-
-
-
-
-
TYP
2.8
26
18
18
12
20
10
10
10
MAX
-
-
-
-
-
-
-
-
-
UNITS
V
ns
ns
ns
ns
ns
ns
ns
ns
Diode Braking Holdoff Time (Note 4)
t UG_OFF_DB V VCC = 12V
-
60
-
ns
Minimum LGATE ON-Time At Diode Emulation
t LG_ON_DM
V VCC = 12V
230
330
450
ns
OUTPUT (Note 4)
Upper Drive Source Current
I U_SOURCE
V VCC = 12V, 3nF Load
-
1.25
-
A
Upper Drive Source Impedance
R U_SOURCE 20mA Source Current
-
2.0
-
Ω
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
I U_SINK
R U_SINK
I L_SOURCE
V VCC = 12V, 3nF Load
20mA Sink Current
V VCC = 12V, 3nF Load
-
-
-
2
1.35
2
-
-
-
A
Ω
A
Lower Drive Source Impedance
R L_SOURCE 20mA Source Current
-
1.35
-
Ω
Lower Drive Sink Current
Lower Drive Sink Impedance
I L_SINK
R L_SINK
V VCC = 12V, 3nF Load
20mA Sink Current
-
-
3
0.90
-
-
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
-
3
3
4
GD_SEL
PWM
This pin sets the LG drive voltage in PSI mode.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section on page 6 for further details. Connect this pin to the PWM output of the
controller.
4
5
6
-
5
6
7
8
GND
LGATE
LVCC
UVCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin provides power to the upper gate drive. Its operating range is +5V to 12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7
9
VCC
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
-
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6470.2
October 30, 2008
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