参数资料
型号: ISL6721AVZ
厂商: Intersil
文件页数: 11/22页
文件大小: 0K
描述: IC REG CTRLR PWM CM 16-TSSOP
标准包装: 96
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 9 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 1243 (CN2011-ZH PDF)
ISL6721
CURRENT SENSE SIGNAL
Current Sense Signal
Downslope
DOWNSLOPE
A resistor divider between V IN and LGND to each input
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Overcurrent Operation
The overcurrent threshold level is set by the voltage applied
at the ISET pin. Setting the overcurrent level may be
accomplished by using a resistor divider network from VREF
Time
TIME
FIGURE 5.
The minimum amount of capacitance to place at the SLOPE
pin is calculated in Equation 6:
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
Overcurrent delayed shutdown is enabled once the soft-start
t ON
C SLOPE = 4.24 × 10
– 6
? -----------------------
V SLOPE
F
(EQ. 6)
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
discharging current source is enabled. The soft-start
where t ON is the On time and V SLOPE is the amount of
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
compensation added is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching Frequency, f sw = 250kHz
Duty Cycle, D = 60%
t ON = D/f sw = 0.6/250E3 = 2.4μs
t OFF = (1 - D)/fsw = 1.6μs
Determine the downslope:
Downslope = 0.125V/1.6μs = 78mV/μs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
capacitor is discharged at a rate of 40μA. At the same time,
a 50μs retriggerable one-shot timer is activated amd it
remains active for 50μs after the overcurrent condition stops.
The soft-start discharge cycle cannot be reset until the one-
shot timer becomes inactive. If the soft-start capacitor
discharges by more than 0.125V to 4.375V, the output is
disabled and the soft-start capacitor is discharged. The
output remains disabled and I CC drops to 200μA for
approximately 295ms. A new soft-start cycle is then initiated.
The shutdown and restart behavior of the OC protection is
often referred to as hic-cup operation due to its repetitive
start-up and shutdown characteristic.
If the overcurrent condition ceases at least 50μs prior to the
soft-start voltage reaching 4.375V, the soft-start charging
and discharging currents revert to normal operation and the
soft-start voltage is allowed to recover.
Hiccup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
V SLOPE = --- ? 0.078 ? 2.4 = 94mV
Therefore,
1
2
(EQ. 7)
voltage, or about 1.5V.
Leading Edge Blanking
The initial 100ns of the current feedback signal input at
C SLOPE ( MIN ) = 4.24 × 10
2.4 × 10
– 6
– 6
? ----------------------- ≈ 110pF
0.094
(EQ. 8)
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68pF and 33pF.
Overvoltage and Undervoltage Monitor
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
I CC , is reduced to 200μA for ~295ms at which time recovery
is attempted. If the fault is cleared, a soft-start cycle begins.
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
11
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the
overcurrent comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~+130°C. When a
Fault is detected the GATE output is disabled and the
soft-start capacitor is quickly discharged. When the Fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
FN9110.6
March 5, 2008
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