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参数资料
| 型号： | ISL6721EVAL3Z |
| 厂商： | Intersil |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 3 FOR ISL6721 |
| 标准包装： | 1 |
| 系列： | * |
ISL6721
minimum V IN , maximum load, maximum C OUT , and
minimum ESR.
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, V IN = 48V
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
I OUT (A), 3.3V
0
I OUT (A), 1.8V V OUT (V), 3.3V V OUT (V), 1.8V
0.030 3.351 1.825
to about f sw /4. For this example, the bandwidth will be further
limited due to the low GBWP of the LM431-based Error
Amplifier and the opto-coupler. A bandwidth of approximately
5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C 14 is an integrating capacitor). The first
zero is placed below the crossover frequency, f co , usually
around 1/3 f co . The second pole is placed at the lower of the
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R 17 = R 18 = R 15 = 1k Ω
R 20 = open
C 13 = 100nF
C 14 = 100pF
A Bode plot of the closed loop system at low line, max load
appears in Figures 9A and 9B.
50
40
30
20
10
0
-10
-20
-30
-40
-50
0.39
0.88
1.38
1.87
2.39
2.89
3.37
0
0.39
0.88
1.38
1.87
2.39
2.89
0
0.39
0.88
1.38
1.87
2.39
0
0.39
0.88
1.38
1.87
0
0.39
0.88
0.030
0.030
0.030
0.030
0.030
0030
0.030
0.52
0.52
0.52
0.52
0.52
0.52
0.52
1.05
1.05
1.05
1.05
1.05
1.05
1.55
1.55
1.55
1.55
1.55
2.07
2.07
2.07
3.281
3.251
3.223
3.204
3.185
3.168
3.153
3.471
3.283
3.254
3.233
3.218
3.203
3.191
3.619
3.290
3.254
3.235
3.220
3.207
3.699
3.306
3.260
3.239
3.224
3.762
3.329
3.270
1.956
1.988
2.014
2.029
2.057
2.084
2.103
1.497
1.800
1.836
1.848
1.855
1.859
1.862
1.347
1.730
1.785
1.805
1.814
1.820
1.265
1.682
1.750
1.776
1.789
1.201
1.645
1.722
10k
100k
1M
10M
100M
1.38
2.07
3.245
1.752
200
150
FREQUENCY (Hz)
FIGURE 9A. GAIN
0
0.39
0.88
0
0.39
2.62
2.62
2.62
3.14
3.14
3.819
3.355
3.282
3.869
3.383
1.142
1.612
1.697
1.091
1.581
100
50
0
-50
Waveforms
Typical waveforms can be found in Figures 10 through 12.
Figure 10 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2), the SYNC output
-100
10k
100k
1M
10M
100M
pulse (Trace 1), and the GATE output to the converter FET
(Trace 3). Figure 11 shows the converter behavior while
FREQUENCY (Hz)
FIGURE 9B. PHASE MARGIN
17
operating in an overcurrent fault condition. Trace 1 is the
soft-start voltage, which increases from 0V to 4.5V, at which
point the OC fault function is enabled. The OC condition is
detected and the soft-start capacitor is discharged to the
FN9110.6
March 5, 2008
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