参数资料
型号: ISL6722AABZ
厂商: Intersil
文件页数: 17/24页
文件大小: 0K
描述: IC REG CTRLR PWM CM 16-SOIC
标准包装: 960
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 9 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
ISL6722A, ISL6723A
For purposes of this discussion we will assume the following:
3.3V output: 100mV total output ripple and noise
ESR: 60mV
Capacitor Δ Q: 10mV
ESL: 30mV
1.8V output: 50mV total output ripple and noise
amount of gain variation due the current transfer ratio (CTR).
The CTR of the opto-coupler varies with initial tolerance,
temperature, forward current, and age.
A block diagram of the feedback control loop follows in
Figure 10.
PRIMARY SIDE AMPLIFIER
ESR: 30mV
Capacitor Δ Q: 5mV
Z3
REF +
-
PWM
POWER
STAGE
VOUT
ESL: 15mV
For the 3.3V output:
Z4
ERROR AMPLIFIER
ESR ≤ ----------------------------- = = 7.3m Ω
Δ V 0.060
Ispk – Iout 10.73 – 2.5
-----------------------------
(EQ. 35)
ISOLATION
Z2
The change in voltage due to the change in charge of the
output capacitor, Δ Q, determines how much capacitance is
required on the output.
-
+
REF
Z1
( 10.73 – 2.5 ) ? 2.33 × 10
( Ispk – Iout ) ? Tr
C ≥ ---------------------------------------------- = ------------------------------------------------------------------- = 960 μ F
– 6
2 ? Δ V 2 ? 0.010
(EQ. 36)
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L ? di/dt).
FIGURE 10.
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
0.030 ? 200 × 10
V ? dt
– 9
L ≤ --------------- = ---------------------------------------------- = 0.56nH
di 10.73
(EQ. 37)
precaution in case operation in continuous mode should
occur at some operating point.
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as
surface mount ceramic or film are connected in parallel with
the high capacitance capacitors to address the effects of
ESL. A combination of high frequency and high ripple
capability capacitors is used to achieve the desired overall
performance. The analysis of the 1.8V output is similar to
VERROR
-
VOUT
that of the 3.3V output and is omitted for brevity. Two
OSCON 4SEP560M (560μF) electrolytic capacitors and a
22μF X5R ceramic 1210 capacitor were selected for both the
3.3V and 1.8V outputs. The 4SEP560M electrolytic
+
REF
capacitors are each rated at 4520mA ripple current and
13m Ω of ESR. The ripple current rating of just one of these
capacitors is adequate, but two are needed to meet the
minimum ESR and capacitance values.
The bias output is of such low power and current that it
places negligible stress on its filter capacitor. A single 0.1μF
ceramic capacitor was selected.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6722A. The opto-coupler is used
to transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the
isolation barrier, but it adds complexity to the feedback
control loop. It adds a pole at about 10kHz and a significant
17
FIGURE 11. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode
control is rather complex. The method of preference [1] was
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled as
a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
FN9237.1
July 11, 2007
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ISL6722AABZ-T 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6722AARZ 功能描述:IC REG CTRLR BST FLYBK ISO 16QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6722AARZ-T 功能描述:IC REG CTRLR BST FLYBK ISO 16QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6722AAVZ 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6722AAVZ-T 功能描述:IC REG CTRLR PWM CM 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)