参数资料
| 型号： | ISL6723AABZ |
| 厂商： | Intersil |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-SOIC |
| 标准包装： | 960 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
ISL6722A, ISL6723A
Figure 6 depicts overcurrent behavior during soft-start.
ISENSE’ represents the scaled values of ISENSE at the
input to the overcurrent comparator.
4.5 V
SS
ISET
ISENSE
GATE
FIGURE 6. PULSE-BY-PULSE OC BEHAVIOR DURING SS
Although an overcurrent condition exists, a shutdown is not
allowed prior to completion of the SS cycle. Only peak
current limit operates during the soft-start cycle. If the
overcurrent condition were to continue beyond the soft-start
cycle, a delayed overcurrent shutdown would occur as
shown in Figure 7:
causing false trips of the PWM comparator and the
overcurrent comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, or the UV input falls below 1.45V.
When a Fault is detected, the GATE output is disabled and
the soft-start capacitor is quickly discharged. When the Fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
connected at a single point. V C should be bypassed directly
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
SS
4.5 V
Reference Design
ISET
4.375V
GND
295ms
The Typical Application Schematic features the ISL6722A in
a conventional dual output 10W discontinuous mode flyback
DC/DC converter. The ISL6722AEVAL1 demonstration unit
implements this design and is available for evaluation.
ISENSE'
The input voltage range is from 36 to 75V DC, and the two
GATE
FIGURE 7. OC SHUTDOWN BEHAVIOR
If the overcurrent condition is removed prior to a shutdown, a
recovery can occur as indicated in Figure 8. When the load
decreases below the overcurrent threshold and an additional
50μs elapses without the SS dropping below 4.375V, the
overcurrent circuitry resets and the soft-start voltage
recovers.
outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross regulation
is achieved using the weighted sum of the two outputs.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C 1 , C 2 , C 3
Isolation Transformer: T1
Primary voltage Clamp: C R6 , R 24 , C 18
SS
OC
4.5V
50ms
Start Bias Regulator: R 1 , R 2 , R 6 , Q 3 , V R1
Operating Bias and Regulator: R 25 , Q 2 , D 1 , C 5 , C R2 , D 2
4.375V
ISET
ISENSE'
GATE
FIGURE 8. OC RECOVERY PRIOR TO SHUTDOWN
Leading Edge Blanking
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
13
Main MOSFET Power Switch: Q 1
Current Sense Network: R 4 , R 3 , R 23 , C 4
Feedback Network:, R 13 , R 15 , R 16 , R 17 , R 18 , R 19 , R 20 ,
R 26 , R 27 , C 13 , C 14 , U 2 , U 3
Control Circuit: C 7 , C 8 , C 9 , C 10 , C 11 , C 12 , R 5 , R 6 , R 8 , R 9 ,
R 10 , R 11 , R 12 , R 14 , R 22
Output Rectification and Filtering: C R4 , C R5 , C 15 , C 16 , C 19 ,
C 20 , C 21 , C 22
Secondary Snubber: R 21 , C 17
FN9237.1
July 11, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6726AAZ-T7A | IC REG CTRLR ISO PWM CM 20-QSOP |
| ISL6729IU-T | IC REG CTRLR BST FLYBK ISO 8MSOP |
| ISL6740AIVZA | IC REG CTRLR PWM VM 16-TSSOP |
| ISL6741IV-T | IC REG CTRLR PWM CM 16-TSSOP |
| ISL6742AAZA-T | IC REG CTRLR PWM CM/VM 16-QSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6723AABZ-T | 功能描述:IC REG CTRLR PWM CM 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6726AAZ | 功能描述:IC REG CTRLR ISO PWM CM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL6726AAZ-T | 功能描述:IC REG CTRLR ISO PWM CM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6726AAZ-T7A | 功能描述:IC REG CTRLR ISO PWM CM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6726EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL6726 EVALUATION BOARD 1 - 20 LD QSOP - ROHS COMPLIAN - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR ISL6726 制造商:Intersil Corporation 功能描述:ISL6726 EVALUATION BOARD 1 - 20 Ld QSOP - ROHS COMPLIAN |
发布紧急采购，3分钟左右您将得到回复。