参数资料
| 型号： | ISL6723AABZ |
| 厂商： | Intersil |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-SOIC |
| 标准包装： | 960 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 9 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
ISL6722A, ISL6723A
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
integration characteristic which results in excellent DC
the remaining pole and zero for the compensator are located
at:
f pc = ------------------------------------------------------------ ≈ --------------------------------------------
f zc = --------------------------------------------
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, A EXT , of 0.5 V/A was
selected to achieve this.
C 13 + C 14 1
2 ? π ? R 15 ? C 14 ? C 13 2 ? π ? R 15 ? C 14
1
2 ? π ? R 15 ? C 13
(EQ. 40)
(EQ. 41)
ISET = 2.25 ? 0.8 ? 0.5 + 0.100 = 1.00
V
(EQ. 38)
The control to output transfer function may be represented
as [2].
The ratio of R 15 to the parallel combination of R 17 and R 18
determine the mid band gain of the error amplifier.
1 + ------
v o R o ? L s ? f sw ω z
v c
1 + -------
R 17 ? R 18
s
------ = K ? --------------------------------- ? -----------------
2 s
ω p
(EQ. 39)
R 15 ? ( R 17 + R 18 )
A midband = ------------------------------------------------
(EQ. 42)
From Equation 27, it can be seen that the control to output
I spk ( max )
if we ignore the current feedback sampled-data effects:
K = --------------------------
V c ( max )
R o = LoadResis tan ce
L s = SecondaryInduc tan ce
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum Vin, maximum load, maximum C OUT , and
minimum ESR.
ω p = --------------------
f p = -----------------------------
ω z = --------------------
f z = --------------------------------------
2
R o ? C o
1
R c ? C o
or
or
1
π ? R o ? C o
1
2 ? π ? R c ? C o
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about f sw /4. For this example, the bandwidth
C o = OutputCapaci tan ce
R c = OutputCapaci tan ceE SR
V c ( max ) = ControlVoltageRange
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15W, so:
will be further limited due to the low GBWP of the
LM431-based Error Amplifier and the opto-coupler. A
bandwidth of approximately 5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C 14 is an integrating capacitor). The first
zero is placed below the crossover frequency, f co , usually
around 1/3 f co . The second pole is placed at the lower of the
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
P out
2 ? ------------ ? tsw 15
2 ? -------- ? 5 × 10
I spk ( max ) = ------------------------------------- = ------------------------------------------ = 19.5
2.33 × 10
v c ( max ) = V ISENSE ? A EXT ? A CS ? --------------------- = 2.93
V out 3.3
Tr
– 6
1
A COMP
A
V
Using this technique to determine the compensation, the
following values for the EA components were selected.
R 17 = R 18 = R 15 = 1k Ω
R 20 = open
where A EXT is the external gain of the current feedback
network, A CS is the IC internal gain, and A COMP is the gain
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
18
C 13 = 100nF
C 14 = 100pF
FN9237.1
July 11, 2007
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