参数资料
型号: ISL6740EVAL2
厂商: Intersil
文件页数: 10/28页
文件大小: 0K
描述: EVALUATION BOARD 2 ISL6740
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
功率 - 输出: 96W
输出电压: 12V
电流 - 输出: 8A
输入电压: 36 ~ 75 V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6740
ISL6740, ISL6741
Typical Performance Curves
1.001
1.000
65
60
55
0.999
50
0.998
45
0.997
-40
-25 -10
5
20
35
50
65
80
95 110
40
0
50
100 150 200 250 300 350 400 450 500
TEMPERATURE (°C)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
RTD CURRENT (μA)
FIGURE 2. OSCILLATOR C T DISCHARGE CURRENT GAIN
1?10 4
CT (pF) =
1?10 6
1000
680
470
1?10 3 330
220
100
100
1?10 5
RTD = 10k
CT (pF) =
100
220
330
680
1?10 4
10
10
20
30
40
50
60
70
80
90
100
470
10 20 30
40
50
1000
60
70
80
90
100
RTD (k Ω )
FIGURE 3. DEADTIME (TD) vs CAPACITANCE
Pin Descriptions
VDD - V DD is the power connection for the IC. To optimize noise
immunity, bypass V DD to GND with a ceramic capacitor as close
to the V DD and GND pins as possible.
The total supply current, I DD , will be dependent on the load
applied to outputs OUTA and OUTB. Total I DD current is the sum
of the quiescent current and the average output current. Knowing
the operating frequency, f SW , and the output loading capacitance
charge, Q, per output, the average output current can be
RTC (k Ω )
FIGURE 4. CAPACITANCE vs FREQUENCY
clock with a pulse width less than one-half of the oscillator period
must be used.
RTC - This is the oscillator timing capacitor charge current control
pin. A resistor is connected between this pin and GND. The
current flowing through the resistor determines the magnitude of
the charge current. The charge current is nominally twice this
current. The PWM maximum ON time is determined by the
timing capacitor charge duration.
calculated from:
I OUT = 2 ? Q ? f SW
A
(EQ. 1)
RTD - This is the oscillator timing capacitor discharge current
control pin. A resistor is connected between this pin and GND.
The current flowing through the resistor determines the
SYNC - A bidirectional synchronization signal used to coordinate
the switching frequency of multiple units. Synchronization may
be achieved by connecting the SYNC signal of each unit together
or by using an external master clock signal. The oscillator timing
capacitor, C T , is always required regardless of the
synchronization method used. The paralleled unit with the
highest oscillator frequency assumes control. Self-
synchronization is not recommended for oscillator frequencies
above 900kHz. For higher switching frequencies, an external
10
magnitude of the discharge current. The discharge current is
nominally 50x this current. The PWM deadtime is determined by
the timing capacitor discharge duration.
CT - The oscillator timing capacitor is connected between this pin
and GND.
VERROR - The inverting input of the PWM comparator. The error
voltage is applied to this pin to control the duty cycle. Increasing
the signal level increases the duty cycle. The node may be driven
with an external error amplifier or opto-coupler.
FN9111.6
December 2, 2011
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