参数资料
型号: ISL6740IBZ
厂商: INTERSIL CORP
元件分类: 稳压器
英文描述: Flexible Double Ended Voltage and Current Mode PWM Controllers
中文描述: 0.5 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16
封装: ROHS COMPLIANT, PLASTIC, MS-012-AC, SOIC-16
文件页数: 15/29页
文件大小: 635K
代理商: ISL6740IBZ
22
FN9111.4
July 13, 2007
Adding Line Only Regulation - Feed Forward
Output voltage variation caused by changes in the supply
voltage may be virtually removed through a technique known
as feed forward compensation. Using feed forward, the duty
cycle is directly controlled based on changes in the input
voltage only. No closed loop feedback system is required.
Voltage feed forward may be implemented as shown in
Figure 18..
The circuit provides feed forward compensation for a 2:1
input voltage range. Resistors R100 and R101 set the input
voltage divider to generate a 1V signal at the input voltage
that corresponds to maximum duty cycle (VIN minimum).
Resistors R109, R110, and R111 form a voltage divider from
VREF to create reference voltages for the amplifiers. The
first stage uses U100A, R102, R103, R104, and C100 to form
a unity gain inverting amplifier. Its output varies inversely
with input voltage and ranges from 1V to 2V. The bandwidth
of the circuit may be controlled by varying the value of C100.
The gain of the first amplifier stage is:
where:
VA = Output voltage of U100A
VD = The input divider voltage
The second stage uses U100B, R105, R106, R107, and R108
to form a summing amplifier which offsets the first stage
output by 0.8V (the value of CT valley voltage). The signal
applied to the VERROR input now matches the offset and
amplitude of the oscillator sawtooth so that the duty cycle
varies linearly from 100% to 50% of maximum with a 2:1
input voltage variation.
Other duty ranges are possible, but are still limited to a 2:1
ratio. The voltage applied to VERROR must be scaled to the
peak-to-peak voltage on CT, and offset by the valley voltage.
Since the peak-to-peak CT voltage is 2.00V nominal, the
voltage at the output of U100A must be divided by 2.0V to
obtain the desired duty cycle. For example, if an 80% duty
cycle was required at the minimum operating voltage, the
output of U100A must be 1.60V (80% of 2.00V). From
(Equation 25), the divider voltage must be set to 1.4V for the
input voltage that corresponds to the 80% duty cycle.
It should be noted that the synchronous rectifiers (SRs),
being driven from the transformer secondary, are only gated
on during the ON time of the primary FETs. Conduction
continues through the body diodes during the OFF time
when operating in continuous inductor current mode. This
mode of operation usually results in significant conduction
and switching losses in the SR FETs. These losses may be
reduced considerably by either adding schottky diodes in
parallel to the SR FETs or by driving the SR FETs directly
with a control signal.
Adding Regulation - Closed Loop Feedback
The second Typical Application schematic adds closed loop
feedback with isolation. The ISL6740EVAL2Z demonstration
platform implements this design and is available for
evaluation. The input voltage range was increased to 36V to
75V, which necessitates a few modifications to the open loop
design. The output inductor value was increased to 4.0
μH,
schottky rectifier CR4 was added to minimize SR FET body
diode conduction, the turns ratio of the main transformer was
changed to 4:3, and the synchronous rectifier gate drives
were modified. The design process is essentially the same
as it was for the unregulated version, so only the feedback
control loop design will be discussed.
The major components of the feedback control loop are a
programmable shunt regulator and an opto-coupler. The
opto-coupler is used to transfer the error signal across the
isolation barrier. The opto-coupler offers a convenient means
to cross the isolation barrier, but it adds complexity to the
feedback control loop. It adds a pole at about 10kHz and a
significant amount of gain variation due the current transfer
ratio (CTR). The CTR of the opto-coupler varies with initial
tolerance, temperature, forward current, and age.
FIGURE 18. VOLTAGE FEED FORWARD CIRCUIT
+
-
+
-
1.5V
0.8V
R102
100k
R101
2k
R100
69.8k
+VIN
VREF
R109
3.48k
R110
698
R111
806
R104
100k
R106
100K
R105
100k
R107
100k
R108
100k
R103
49.9k
C100
1nF
to VERROR
U100A
U100B
V
A
V
D
3.00
+
=
V
(EQ. 25)
ISL6740, 1SL6741
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