参数资料
型号: ISL6753AAZA
厂商: Intersil
文件页数: 10/15页
文件大小: 0K
描述: IC REG CTRLR PWM CM/VM 16-QSOP
标准包装: 98
PWM 型: 电流/电压模式
输出数: 4
频率 - 最大: 2MHz
占空比: 100%
电源电压: 9 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1243 (CN2011-ZH PDF)
ISL6753
The charging time of the ramp capacitor is
The criteria for determining the correct amount of external
t = – R3 ? C7 ? ln ? 1 – ---------------------------------------- ) ?
? V RAMP ( PEAK ?
? V IN ( MIN ) ?
S
(EQ. 7)
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
For optimum performance, the maximum value of the
capacitor should be limited to 10nF. The maximum DC
current through the resistor should be limited to 2mA
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
Q = -------------------------------------------------
maximum. For example, if the oscillator frequency is
400kHz, the minimum input voltage is 300V, and a 4.7nF
ramp capacitor is selected, the value of the resistor can be
1
π ( m c ( 1 – D ) – 0.5 )
(EQ. 12)
determined by rearranging Equation 7.
where D is the percent of on time during a half cycle. Setting
– 2.5 ? 10
R3 = ------------------------------------------------------------------------- = ------------------------------------------------------------
? ln ? 1 – ---------- ?
? V RAMP ( PEAK ) ?
4.7 ? 10
S e = S n ? ? --- + 0.5 ? ------------- – 1 ?
– t
C7 ? ln ? 1 – ---------------------------------------- ? ? 300 ?
? V IN ( MIN ) ) ?
– 9 1
– 6
Q = 1 and solving for Se yields:
1 1
? ? π ? 1 – D ?
(EQ. 13)
= 159
k ?
(EQ. 8)
Since S n and S e are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
where t is equal to the oscillator period minus the deadtime.
by Ton to obtain the voltage change that occurs during Ton.
V e = V n ? ? --- + 0.5 ? ------------- – 1 ?
If the deadtime is short relative to the oscillator period, it can
be ignored for this calculation.
? ? π ? 1 – D ?
1 1
(EQ. 14)
If feed forward operation is not desired, the RC network may
be connected to VREF rather than the input voltage.
Alternatively, a resistor divider from CTBUF may be used as
the sawtooth signal. Regardless, a sawtooth waveform must
be generated on RAMP as it is required for proper PWM
operation.
where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding:
V e = ------------------------------------------ ? -------- ? --- + D – 0.5 ?
N P ? π
N CT ? L O
Slope Compensation
Peak current-mode control requires slope compensation to
T SW ? V O ? R CS N S 1
?
V
(EQ. 15)
Fm = --------------------
(EQ. 9)
(EQ. 10)
Fm = --------------------------------------- = ----------------------------
m c SnTsw
N S ? R CS ? D ? T SW ? N S ? ?
V CS = ------------------------ ? I O + --------------------- ? V IN ? -------- – V O ? ?
N P ? N CT ?
V e + V CS = 1
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
1
SnTsw
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
1 1
( Sn + Se ) Tsw
where R CS is the current sense burden resistor, N CT is the
current transformer turns ratio, L O is the output inductance,
V O is the output voltage, and Ns and Np are the secondary
and primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields:
V
2L O ? N P ? ?
(EQ. 16)
where V CS is the voltage across the current sense resistor
and I O is the output current at current limit.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
(EQ. 17)
m c = 1 + Se
N P ? N CT 1
R CS = ------------------------ ? ------------------------------------------------------
I O + -------- T SW ? 1 --- + D - ?
--- ?
L ? π 2
where Se is slope of the external ramp and
-------
Sn
10
(EQ. 11)
Substituting Equations 15 and 16 into Equation 17 and
solving for R CS yields
? (EQ. 18)
N S V O
O
FN9182.2
April 4, 2006
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ISL6753AAZA-T 功能描述:IC REG CTRLR PWM CM/VM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6754AAZA 功能描述:IC REG CTRLR PWM CM/VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6754AAZA-T 功能描述:IC REG CTRLR PWM CM/VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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