参数资料
型号: ISL6753AAZA
厂商: Intersil
文件页数: 12/15页
文件大小: 0K
描述: IC REG CTRLR PWM CM/VM 16-QSOP
标准包装: 98
PWM 型: 电流/电压模式
输出数: 4
频率 - 最大: 2MHz
占空比: 100%
电源电压: 9 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1243 (CN2011-ZH PDF)
ISL6753
If the application requires deadtime less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400ns. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
CT
DEADTIME
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
OUTLL
OUTLR
PWM
PWM
PWM
PWM
1
2
3
4
5 CT
ISL6753
VREF 16
15
14
13
12
OUTUR
OUTUL
RESDEL
WINDOW
RESONANT
DELAY
R9
6
7
11
10
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
R6
8 CS
9
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
R CS
C4
CT
VIN+
UL
UR
D1
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
L L
VOUT+
RTN
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 21
and 22 require modification. Equation 21 becomes:
VIN-
LL
LR
D2
V e – ? V CS = ----------------------
2D ? R6
R6 + R9
V
(EQ. 25)
FIGURE 10. IDEALIZED FULL-BRIDGE
In Figure 10, the power semiconductor switches have been
and Equation 22 becomes:
replaced by ideal switch elements with parallel diodes and
( 2D – V e + ? V CS ) ? R6
V e – ? V CS
R9 = -------------------------------------------------------------
?
(EQ. 26)
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
ZVS Full-Bridge Operation
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
12
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 11, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I P and I S , respectively.
FN9182.2
April 4, 2006
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ISL6753AAZA-T 功能描述:IC REG CTRLR PWM CM/VM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6754AAZA 功能描述:IC REG CTRLR PWM CM/VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL6754AAZA-T 功能描述:IC REG CTRLR PWM CM/VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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