参数资料
| 型号： | ISL6884IAZ |
| 厂商： | Intersil |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR CCFL BRIGHTNESS 20-SSOP |
| 标准包装： | 580 |
| 显示器类型： | CCFL - 冷色阴极荧光灯 |
| 接口： | I²C |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
ISL6884
Register Description Table
Register Descriptions:
NOTES:
1. sb denotes sign bit for 2’s compliment numbers.
2. The second row shows the register ’s default value loaded at Power On Reset.
TABLE 1. REGISTER DESCRIPTION TABLE (READ/WRITE REGISTERS)
WORD NAME
BYTE
DESCRIPTION
ADDRESS
POR
MSB LABEL
POR VALUE
BIT 6 LABEL
POR VALUE
BIT 5 LABEL
POR VALUE
BIT 4 LABEL
POR VALUE
BIT 3 LABEL
POR VALUE
BIT 2 LABEL
POR VALUE
BIT 1 LABEL
POR VALUE
LSB LABEL
POR VALUE
BRT_M
Brightness Magnitude Setting
0x00
POR
b7
0
b6
0
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
brt_os1
Brightness Offset for Light Sensor 1. Note: Value is stored as 2’s complement number
0x01
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os2
Brightness Offset for Light Sensor 2. Note: Value is stored as 2’s complement number.
0x02
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os3
Brightness Offset for Light Sensor 3. Note: Value is stored as 2’s complement number
0x03
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os4
Brightness Offset for Light Sensor 4. Note: Value is stored as 2’s complement number.
0x04
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os5
Brightness Offset for Light Sensor 5. Note: Value is stored as 2’s complement number
0x05
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os6
Brightness Offset for Light Sensor 6. Note: Value is stored as 2’s complement number.
0x06
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os7
Brightness Offset for Light Sensor 7. Note: Value is stored as 2’s complement number.
0x07
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
brt_os8
Brightness Offset for Light Sensor 8. Note: Value is stored as 2’s complement number.
0x08
sb
b4
b3
b2
b1
b0
POR
0
0
0
0
0
0
0
0
mstr_en
0x2a
Master Enable, This signal is AND’ed with the en pin to create the enable for the PWM dimming output.
mstr_en
POR
0
0
0
0
0
0
0
0
ch_en
Individual Channel Enables for each DPWM output.
0x2b
POR
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
flt_tout
Fault Timer Time Out Setting.
8
FN9265.0
March 9, 2006
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