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参数资料
| 型号： | ISL76683AROZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 9/17页 |
| 文件大小： | 0K |
| 描述： | DIGITAL LIGHT SENSOR ADC 6ODFN |
| 标准包装： | 1 |
| 带接近传感器： | 无 |
| 波长： | 540nm |
| 电源电压： | 2.5 V ~ 3.3 V |
| 输出类型： | I²C? |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | ISL76683AROZ-T7DKR |
ISL76683
ADDRESS
TABLE 2. WRITE ONLY REGISTERS
REGISTER FUNCTIONS/
NAME DESCRIPTION
4. Photodiode Select Mode; Bits 3 and 2. This function controls
the mux attached to the two photodiodes. At Mode1, the mux
directs the current of Diode1 to the ADC. At Mode2, the mux
directs the current of Diode2 only to the ADC. Mode3 is a
b1xxx_xxxx
sync_iic
Writing a logic 1 to this address bit ends
the current ADC-integration and starts
another. Used only with External Timing
Mode.
sequential Mode1 and Mode2 with an internal subtract
function (Diode1 - Diode2).
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
bx1xx_xxxx
clar_int
Writing a logic 1 to this address bit clears
the interrupt.
BITS 3:2
0:0
MODE
MODE1. ADC integrates or converts Diode1 only. Current
is converted to an n-bit unsigned data.*
Command Register 00(hex)
The Read/Write command register has five functions:
1. Enable; Bit 7. This function either resets the ADC or enables
the ADC in normal operation. A logic 0 disables ADC to reset
mode. A logic 1 enables ADC to normal operation.
0:1
1:0
1:1
MODE2. ADC integrates or coverts Diode2 only. Current is
converted to an n-bit unsigned data.*
MODE3. A sequential MODE1 then MODE2 operation.
The difference current is an (n-1) signed data.*
No Operation.
TABLE 3. ENABLE
*n = 4, 8, 12,16 depending on the number of clock cycles
BIT 7
0
1
OPERATION
Disable ADC-Core to Reset-Mode (default)
Enable ADC-Core to Normal Operation
function.
5. Width; Bits 1 and 0. This function determines the number of
clock cycles per conversion. Changing the number of clock
cycles does more than just change the resolution of the
device; it also changes the integration time, which is the
2. ADCPD; Bit 6. This function puts the device in a power-down
mode. A logic 0 puts the device in normal operation. A logic 1
powers down the device.
period the device’s analog-to-digital (A/D) converter samples
the photodiode current signal for a lux measurement.
TABLE 7. WIDTH
TABLE 4. ADCPD
BITS 1:0
NUMBER OF CLOCK CYCLES
BIT 6
0
1
OPERATION
Normal Operation (default)
Power-Down
0:0
0:1
1:0
2 16 = 65,536
2 12 = 4,096
2 8 = 256
For proper shut down operation, it is recommended to disable
1:1
2 4 = 16
ADC first then disable the chip. Specifically, the user should first
send I 2 C command with Bit 7 = 0 and then send I 2 C command
with Bit 6 = 1.
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an internal dual
speed oscillator (f OSC ), and the n-bit (n = 4, 8, 12,16) counter
inside the ADC. In External Timing Mode, integration time is
Control Register 01(hex)
The Read/Write control register has three functions:
1. Interrupt flag; Bit 5. This is the status bit of the interrupt. The
bit is set to logic high when the interrupt thresholds have been
triggered, and logic low when not yet triggered.
TABLE 8. INTERRUPT FLAG
determined by the time between two consecutive external-sync
sync_iic pulse commands.
TABLE 5. TIMING MODE
BIT 5 OPERATION
0
Internal Timing Mode. Integration time is internally
timed determined by f OSC , REXT, and number of clock
cycles.
1
External Timing Mode. Integration time is externally
timed by the I 2 C host.
BIT 5
0
1
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
9
FN7697.7
March 24, 2014
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