参数资料
| 型号： | ISL78205AVEZ |
| 厂商： | Intersil |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 20HTSSOP |
| 标准包装： | 740 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 3 V ~ 40 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 两者兼有 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 20-HTSSOP |
ISL78205
Figure 20 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and
H28dB gain margin.
false PGOOD reporting. At start-up when VCC rise from 0, PGOOD
will be pulled low when VCC reaches 1V. After EN pulled low and
VCC falling, PGOOD internal open drain transistor will open with
high impedance when VCC falls below 1V. The time between EN
80
60
40
20
0
-20
-40
LOOP GAIN
pulled low and PGOOD OPEN depends on the VCC falling time to
1V.
In non-synchronous buck application, the phase node will show
normal oscillations after high-side turns off due to oscillations
among the parasitic capacitors at phase node. PGOOD signal
could falsely dip due to this ringing. So in non-synchronous buck
application when PGOOD function is used, an RC snubber
(suggesting 200 ? and 2.2nF as typical) at phase node is highly
recommended to reduce this ringing in order for correct function
of PGOOD.
Layout Suggestions
-60
100
1k
10k
FREQUENCY (Hz)
100k
1M
1. Place the input ceramic capacitors as close as possible to the
IC VIN pin and power ground connecting to the power MOSFET
or diode. Keep this loop (input ceramic capacitor, IC VIN pin
and MOSFET/Diode) as tiny as possible to achieve the least
180
160
140
120
100
80
60
40
PHASE MARGIN
voltage spikes induced by the trace parasitic inductance.
2. Place the input aluminum capacitors close to the IC VIN pin.
3. Keep the phase node copper area small, but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors also close
to the power stage components.
5. Put vias (20 recommended) in the bottom pad of the IC. The
bottom pad should be placed in the ground copper plane with
area as large as possible in multiple layers to effectively
reduce the thermal impedance.
6. Place the 4.7μF ceramic decoupling capacitor at the VCC pin
20
0
100
1k
10k
100k
1M
and as close as possible to the IC. Put multiple vias ( ≥ 3) close
to the ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
FREQUENCY (Hz)
FIGURE 20. SIMULATED LOOP GAIN
PGOOD
The PGOOD pin is output of an open drain transistor (refer to at
pulled up to VCC for proper PGOOD function. At startup, PGOOD
will be turned HIGH (internal PGOOD open drain transistor is
turned off) with 1000 cycles delay after soft start is finished (soft
start ramp reaching 1.02V) and FB voltage is within OV/UV
window(90%REF<FB<110%REF).
At normal operation, PGOOD will be pulled low with no delay if
any of the OV (110%) or UV (90%) comparator is tripped. The
PGOOD will be released HIGH with 1000 cycle delay after FB
recovers to be within OV/UV window(90%REF<FB<110%REF).
When EN is pulled low or VCC is below POR, PGOOD is pulled low
with no delay.
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as
17
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the load for
tighter regulation.
10. Put all the peripheral control components close to the IC.
FIGURE 21. PCB VIA PATTERN
FN7926.3
February 19, 2014
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| ISL78205AVEZ-T | 功能描述:IC REG BUCK SYNC ADJ 20HTSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
| ISL78205AVEZ-TR5303 | 制造商:Intersil Corporation 功能描述:HARMAN BECKER ISL78205AVEZ-T W/SPECIAL CHANGE CONTROL, 12 MO - Tape and Reel |
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| ISL78208ARZ-T | 制造商:Intersil Corporation 功能描述:ISL78208ARZ AUTOMOTIVE GRADE 3A STANDARD BUCK REGULATOR - 5X - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG BUCK SYNC ADJ 3A 32-QFN 制造商:Intersil Corporation 功能描述:DC-DC CONV, BUCK, ADJ, 2MHZ, QFN-32, Primary Input Voltage:28V, No. of Outputs:2, Output Current:3A, No. of Pins:32, Operating Temperature Min:-40C, Operating Temperature Max:105C, Package / Case:32-QFN , RoHS Compliant: Yes |
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