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参数资料
| 型号： | ISL78228ARZ-T |
| 厂商： | Intersil |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ DL 10-DFN |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.75 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 包装： | * |
| 供应商设备封装： | * |
ISL78228
Pin Configuration
ISL78228
(10 LD 3X3 DFN)
TOP VIEW
FB1
1
10 FB2
EN1
2
9
EN2
VIN
LX1
NC
3
4
5
PAD
8
7
6
PG
LX2
SYNC
Pin Descriptions
DFN
1
2
3
4
5
6
7
8
9
10
-
SYMBOL
FB1
EN1
VIN
LX1
NC
SYNC
LX2
PG
EN2
FB2
PAD
DESCRIPTION
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any
voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1
regulator output voltage.
Regulator Channel 1 enable pin. Enable the output, V OUT1 , when driven to high. Shutdown the V OUT1 and discharge output
capacitor when driven to low. Do not leave this pin floating.
Input supply voltage. Connect 10μF ceramic capacitor to power ground.
Switching node connection for Channel 1. Connect to one terminal of inductor for V OUT1 .
Recommended to connect this pin to the exposed pad.
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode.
Connect to an external function generator for Synchronization, and negative edge trigger. Do not leave this pin floating.
Switching node connection for Channel 2. Connect to one terminal of inductor for V OUT2 .
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the V OUT1 and V OUT2 voltages.
There is an internal 1M ? pull-up resistor.
Regulator Channel 2 enable pin. Enable the output, V OUT2 , when driven to high. Shutdown the V OUT2 and discharge output
capacitor when driven to low. Do not leave this pin floating.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any
voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage.
The exposed pad must be connected to PGND for proper electrical performance. Add as much vias as possible for optimal thermal
performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL78228ARZ
8228
PART
MARKING
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
L10.3x3C
PKG.
DWG. #
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78228 . For more information on MSL please see techbrief TB363 .
3
FN7849.2
December 4, 2013
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