参数资料
| 型号： | ISL80112IRAJZ |
| 厂商： | Intersil |
| 文件页数： | 13/17页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 2A 10-DFN |
| 标准包装： | 100 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 3.3 V |
| 输入电压： | 1 V ~ 3.6 V |
| 电压 - 压降（标准）： | 0.053V @ 2A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 2A（最小值） |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 管件 |
ISL80111, ISL80112, ISL80113
See Figure 35 for maximum continuous power dissipation
guidance for ambient temperature and linear air flow rate. This
graph ignores the insignificant power dissipation contribution of
the BIAS pin.
External Capacitor
Requirements
External capacitors are required for proper operation. To ensure
46
44
42
40
38
36
optimal performance, careful attention must be paid to the
layout guidelines and selection of capacitor type and value.
34
2
4
6 8 10 12 14 16 18 20 22
2
EPAD-MOUNT COPPER LAND AREA ON PCB (mm )
24
Input Capacitor
The minimum input capacitor required for proper operation is
10μF with a ceramic dielectric. This minimum capacitor must be
connected to the V IN and ground pins of the LDO no further than
0.5cm away.
Output Capacitor
The ISL8011x applies state-of-the-art internal compensation to
simplify selection of the output capacitor. Stable operation over
the full temperature range, V IN range, V OUT range, and load
extremes is guaranteed for all capacitor types and values,
assuming a 1μF X5R/X7R is used for local bypass on V OUT . This
minimum capacitor must be connected to the V OUT and ground
pins of the LDO no further than 0.5cm away.
Lower-cost Y5V and Z5U type ceramic capacitors are acceptable,
if the size of the capacitor is larger, to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value, in ceramic, POSCAP, or alum/tantalum
electrolytic types, can be placed in parallel to improve PSRR at
higher frequencies or load-transient AC output voltage
tolerances.
Bias Capacitor
The minimum input capacitor required for proper operation is
1μF with a ceramic dielectric. This minimum capacitor must be
connected to the V BIAS and ground pins of the LDO no further
than 0.5cm away. When the VBIAS pin is connected to the V IN
pin, a total of 10μF of X5R/X7R connected to the V IN pin and
ground is sufficient.
Power Dissipation and Thermals
Power Dissipation
Junction temperature must not exceed the range specified in the
“Recommended Operating Conditions” section on Page 4. Power
dissipation can be calculated with Equation 3.
P D = ( V IN – V OUT ) × I OUT + V BIAS × IQ ( BIAS ) + V IN × IQ ( V IN )
(EQ. 3)
The maximum allowable junction temperature, T J(MAX) , and the
maximum expected ambient temperature, T A(MAX) , determine
the maximum allowable power dissipation, as shown in
Equation 4, where θ JA is the junction-to-ambient thermal
resistance.
FIGURE 37. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θ JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
For safe operation, ensure that power dissipation calculated in
Equation 3 (P D ) is less than the maximum allowable power
dissipation, P D(MAX) .
The DFN package uses the copper area on the PCB as a heat
sink. For heat sinking, the EPAD of this package must be
soldered to the copper plane (GND plane). Figure 37 shows a
curve for the θ JA of the DFN package for different copper area
sizes.
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
Filling the thermal pad area with vias is recommended. A typical
via array is to fill the thermal pad footprint with vias spaced such
that they are center on center 3x the radius apart from each
other. Keep the vias small but not so small that their inside
diameter prevents solder from wicking through the holes during
reflow.
FIGURE 38. PCB VIA PATTERN
Connect all vias to the round plane. For efficient heat transfer, it
is important that the vias have low thermal resistance. Do not
use “thermal relief” patterns to connect the vias. It is important
to have a complete connection of the plated through-hole to each
plane.
P D ( MAX ) = ( T J ( MAX ) – T A ) ? θ JA
13
(EQ. 4)
FN7841.2
November 1, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL80112IRAJZ-T | 功能描述:IC REG LDO ADJ 2A 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 稳压器拓扑结构:正，固定式或可调式 输出电压:3.3V，2.5 V ~ 11 V 输入电压:6.5 V ~ 45 V 电压 - 压降（标准）:0.9V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小） 电流 - 限制（最小）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-WQFN 裸露焊盘 供应商设备封装:16-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL80112IRAJZ-T7A | 制造商:Intersil Corporation 功能描述:SINGLE 2A ADJUSTABLE VOUT LDO - 3X3 10LD DFN PB-FREE W/ANNEA - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG LDO ADJ 2A 10DFN 制造商:INTERSIL 功能描述:ISL80112 Series 1 - 3.6 V Single 2 A Adj. 0.8 - 3.6 Vout LDO - DFN-10 制造商:Intersil 功能描述:Single, 2A, Adj Vout LDO IC |
| ISL80113EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL80113 EVAL BOARD - 10LD DFN - ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR ISL80113 制造商:Intersil 功能描述:ISL80113 EVAL |
| ISL80113IRAJZ | 功能描述:IC REG LDO ADJ 3A 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:1 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.7V 输入电压:最高 5.5V 电压 - 压降（标准）:0.21V @ 150mA 稳压器数量:1 电流 - 输出:150mA 电流 - 限制（最小）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 供应商设备封装:TSOT-23-5 包装:剪切带 (CT) 产品目录页面:1100 (CN2011-ZH PDF) 其它名称:576-1852-1 |
| ISL80113IRAJZ-T | 功能描述:IC REG LDO ADJ 3A 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 稳压器拓扑结构:正，固定式或可调式 输出电压:3.3V，2.5 V ~ 11 V 输入电压:6.5 V ~ 45 V 电压 - 压降（标准）:0.9V @ 400mA 稳压器数量:1 电流 - 输出:400mA（最小） 电流 - 限制（最小）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-WQFN 裸露焊盘 供应商设备封装:16-TQFN-EP（5x5） 包装:带卷 (TR) |
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