参数资料
| 型号： | ISL80121IR50Z |
| 厂商： | Intersil |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 1A 10DFN |
| 标准包装： | 100 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 最高 6V |
| 电压 - 压降（标准）： | 0.09V @ 1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1A（最小值） |
| 电流 - 限制（最小）： | 660mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 管件 |
ISL80121-5
1.7
1.5
1.3
1.1
0.9
V IN . PG goes low when the output voltage drops below 84% of the
nominal output voltage, the current limit faults, or the input voltage is
too low. PG functions during shutdown, but not during thermal
shutdown. For applications not using this feature, connect this pin to
ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2μA current source charges up this
0.7
2 20
R SET (k ? )
FIGURE 11. INCREASING I LIMIT (R SET TO GND)
200
C SS and the feedback reference voltage is clamped to the
voltage across it. The start-up time is set by Equation 3:
2 μ A
( C SS x0.5 )
t start = ---------------------------
(EQ. 3)
The current limit can be decreased from the 0.75A default by
tying R SET from the I SET pin to V IN . The current limit is then
determined by both R SET and V IN following Equation 2:
Equation 4 determines the C SS required for a specific start-up
in-rush current, where V OUT is the output voltage, C OUT is the
total capacitance on the output and I INRUSH is the desired in-rush
current.
R SET ( k Ω )
C SS = --------------------------------------------------
2.9 × ( 2 × V IN – 1 )
I LIMIT = 0.75 – -----------------------------------------------
(EQ. 2)
( V OUT xC OUT x2 μ A )
I INRUSH x0.5V
(EQ. 4)
Figure 12 shows the relationship between R SET and the current
limit when R SET is tied from the I SET pin to V IN for V IN = 5.4V.
0.75
0.65
0.55
0.45
0.35
0.25
0.15
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The ISL80121-5 applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, V IN range,
V OUT range and load extremes are guaranteed for all capacitor
types and values assuming a minimum of 10μF X5R/X7R is used
40
0.05
-0.05
R SET (k ? )
400
for local bypass on V OUT . This output capacitor must be
connected to the V OUT and GND pins of the LDO with PCB traces
no longer than 0.5cm.
FIGURE 12. DECREASING I SET (R SET TO V IN )
Enable Operation
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
not be left floating, and should be tied to V IN if not used. A 1k Ω to
10k Ω pull-up resistor is required for applications that use open
collector or open drain outputs to control the ENABLE pin. The
ENABLE pin may be connected directly to V IN for applications
with outputs that are always on.
Power-Good Operation
PG is a logic output that indicates the status of V OUT , current limit
tripping, and V IN . The PG flag is an open-drain NMOS that can
sink up to 10mA during a fault condition. The PG pin requires an
external pull-up resistor typically connected to the V OUT pin. The
PG pin should not be pulled up to a voltage source greater than
8
There is a growing trend to use very-low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients and
also bypass very high frequency noise from other sources. However,
the effective capacitance of MLCCs drops with applied voltage, age,
and temperature. X7R and X5R dieletric ceramic capacitors are
strongly recommended as they typically maintain a capacitance
range within ±20% of nominal voltage over full operating ratings of
temperature and voltage.
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10μF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the V IN and GND pins of the LDO with PCB traces no
longer than 0.5cm.
FN7713.5
June 22, 2012
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