参数资料
| 型号： | ISL8013IRZ |
| 厂商： | Intersil |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 16QFN |
| 产品培训模块： | ISL8013/4 Synchronous Buck Regulators |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 16-QFN（4x4） |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
ISL8013
.
CLOCK
I L
0
PWM
8 CYCLES
PFM
PFM CURRENT LIMIT
LOAD CURRENTT
NOMINAL +1.5%
V OUT
NOMINAL
FIGURE 37. SKIP MODE OPERATION WAVEFORMS
PG
During power-up, the open-drain power good output
holds low for about 1ms after V OUT reaches the
regulation voltage. The PG output also serves as a 1ms
delayed the Power Good signal when the pull-up resistor
R 1 is installed.
Soft Start-Up
bandgap reference and then the soft-start-up begins. It
is recommended that the EN voltage should be kept logic
low (less than 400mV), until V IN reaches 2.5V. Refer to
Figures 38 and 39 for suggested circuit implementation
with V IN slew rate.
VIN
The soft-start-up reduces the inrush current during the
start-up. The soft-start block outputs a ramp reference to
the input of the error amplifier. This voltage ramp limits
2.5V
EN
R 5 ? ( V IN – 1.4V )
R 4 = ---------------------------------------------
the inductor current as well as the output voltage speed
so that the output voltage rises in a controlled fashion.
When VFB is less than 0.2V at the beginning of the soft-
start, the switching frequency is reduced to 1/3 of the
nominal value so that the output can start-up smoothly
at light load condition. During soft-start, the IC operates
in the SKIP mode to support pre-biased output condition.
UVLO
When the input voltage is below the undervoltage
lock-out (UVLO) threshold, the regulator is disabled. To
adjust the voltage level of power on and UVLO, use a
resistive divider across EN. The input voltage
programming resistor R 4 will depend on the bottom
resistor R 5 , as referred to in Figure 38. The value of R 5 is
typically between 10k Ω and 100k Ω .
V IN
R4
<400mV
T t (TIME)
FIGURE 39. CIRCUIT IMPLEMENTATION WITH V IN
SLEW RATE
Let T equal the rise time of V IN . Select the ratio of R 5 and
R 4 such that the voltage is 1.4V (minimum enable logic
high threshold) when V IN is equal to or greater than
2.5V. Set R 5 between 10k Ω to 100k Ω , and use Equation 1
to determine R 4 :
(EQ. 1)
1.4V
Where V IN is greater than or equal to 2.5V.
Then select C such that the equivalent time constant is at
least 2x the rise time, T. This will delay the EN voltage
enough so that the overall EN voltage is less than 400mV
by the time V IN reaches 2.5V. Use Equation 2 to get C:
C ≥ --------------------
EN
1V
R5
C
2 ? T
R 4 || R 5
(EQ. 2)
Where T is the rise time of V IN
FIGURE 38. EXTERNAL RESISTOR DIVIDER
Enable
The enable (EN) input allows the user to control the
turning on or off the regulator for purposes such as
power-up sequencing. When the regulator is enabled,
there is typically a 600μs delay for waking up the
14
As an example, let V IN = 5V with rise time, T = 10ms.
Then R 4 = 56.2k Ω , R 5 = 71.5k Ω , and C = 0.68μF are
used to insure that V IN was >2.5V and the EN voltage
was <400mV.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN
UVLO is set, the outputs discharge to GND through an
internal 100 Ω switch.
FN6309.3
November 23, 2009
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| ISL8013IRZS2715 | 制造商:Intersil Corporation 功能描述:S SPEC FOR TRACKING BROADCOM BUSINESS ONLY-SOLD THRU DISTI - Rail/Tube |
| ISL8013IRZ-T | 功能描述:IC REG BUCK SYNC ADJ 3A 16QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:升压（升压） 输出类型:两者兼有 输出数:1 输出电压:5V，2 V ~ 16.5 V 输入电压:2 V ~ 16.5 V PWM 型:- 频率 - 开关:45kHz 电流 - 输出:50mA 同步整流器:无 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 供应商设备封装:8-PDIP |
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| ISL8014A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:4A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator |
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