参数资料
型号: ISL8013IRZ
厂商: Intersil
文件页数: 16/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 16QFN
产品培训模块: ISL8013/4 Synchronous Buck Regulators
标准包装: 75
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
供应商设备封装: 16-QFN(4x4)
产品目录页面: 1248 (CN2011-ZH PDF)
ISL8013
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
11/23/09
9/10/09
12/27/07
11/27/07
REVISION
FN6309.3
FN6309.2
FN6309.1
FN6309.0
CHANGE
Updated on page 14 in UVLO section, last sentence from “...programming resistor R5..., The
value of R4...” to “...programming resistor R4..., The value of R5...”. Replaced Figure 38,
Removed Equation after Figure 38. Reworded last sentence in Enable section from “It is
necessary to keep the voltage on the EN low until Vin is greater than 2.5V” to “It is
recommended that the EN voltage should be kept logic low (less than 400mV), until VIN
reaches 2.5V. Refer to Figure 39 for suggested circuit implementation with VIN slew rate.
Added Figure 39. Added Equations 1 and 2 and referencing text.
Added Revision History and Products information.
9/10/09:
Page 6, Revised last sentence of EN section from:"Do not leave this pin floating."
TO:"Do not connect directly to VIN or leave this pin floating."
9/2/09:Page 2: Order Info: updated Pb-free note according to lead finish, per Mark Kwoka
Page 3: Revised Block Diagram
Pages 4-5: Per new Intersil standard: Added "Boldface limits apply over the operating
temperature range, -40°C to +85°C." to common conditions of Electrical Specs table. Bolded
MIN MAX columns where applicable. Moved "Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested." from common conditions of Electrical Specs
table to note in Min Max columns.
Page 6: Added following sentence to EN Pin Description:
"Keep the EN voltage low in disabled state until Vin settle or above 2.5V."
Added "Figure 38. EXTERNAL RESISTOR DIVIDER" graphic and following sentence to UVLO
section:"To adjust the voltage level of power on and UVLO, use a resistive divider across EN.
The input voltage programming resistor R5 will depend on on the bottom resistor R4, as
referred to in Figure 38. The value of R4 is typically between 10kohm and 100kohm."
Added Equation 1 to UVLO section:
Added the following sentence to the Enable section:
"It is necessary to keep the voltage of the EN low until Vin is greater than 2.5V."
5/13/08:Added last 2 sentences to paragraph under Table 1. "Additional output capacitance
should be added for better performances in applications where high load transient or low
output ripple is required. It is recommended to check the system level performance along with
the simulation model."
Changed Theta-ja from 37 to 39.
Changed Theta-jc from 6 to 3.
Changed reference of C1 an C2 from "2uF x 22uF" to "2 x 22uF" (In "Typical Operating
Performance" common conditions at header of table)
5/8/08:1. Changed dropout voltage in 2nd paragraph on page 1 from 400mV to 300mV.
2. Added connection between PGND and SGND in Figure 1 on page 2.
Changed Min and Max Values for “Switch Current Limit”, “Peak Skip Limit” and Trans-
Resistance on Page 4.
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell
phones, handheld products, and notebooks. Intersil's product families address power management and analog
signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective
device information page on intersil.com: ISL8013
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
16
FN6309.3
November 23, 2009
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