参数资料
型号: ISL8106CRZ-T
厂商: Intersil
文件页数: 13/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 6,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 电压模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 7 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 带卷 (TR)
ISL8106
For the top-side MOSFET, its switching loss can be written
as:
2 2
V IN ? I VAL ? T ON ? F OSC V IN ? I PEAK ? T OFF ? F OSC
P SWTS ( V IN ) = ------------------------------------------------------------- + ---------------------------------------------------------------------
(EQ. 17)
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V IN at the LX node. The PWM wave is smoothed by the
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
current. The turn-on and turn-off time can be estimated with
the given gate driver parameters in the Electrical
Specification Table.
C COMP1
Selecting The Bootstrap Capacitor
Δ V BOOT
C BOOT = ------------------------
The selection of the bootstrap capacitor can be written as:
Q g
(EQ. 18)
Where:
- Q g is the total gate charge required to switch the top-
side MOSFET
R COMP
COMP
EA
-
+
FB
C COMP2
R TOP
R BOTTOM
- Δ V BOOT , is the maximum allowed voltage decay across
the boot capacitor each time the MOSFET is switched on
As an example, suppose the top-side MOSFET has a total
gate charge Q G , of 25nC at V GS = 5V, and a Δ V BOOT of
200mV. The calculated bootstrap capacitance is 0.125μF;
select at least the first standard component value of greater
capacitance than calculated, that being 0.15μF. Use an X7R
REF
VO
R 3 Modulator FSET
or X5R ceramic capacitor.
Compensating the Converter
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R 3
modulator used in the ISL8106 makes the LC output filter
resemble a first order system in which the closed loop stability
VIN
R FSET
VIN
C FSET
can be achieved with a Type II compensation network.
C COMP1
Q TOP_SIDE
TGATE
C COMP2
R COMP
LX
Gate Drivers
L OUT
DCR
R TOP
FB
?
ISL8106
Q BOTTOM_SIDE C OUT
V REF
ERROR
AMPLIFIER
COMP
GND
BGATE
ESR
FIGURE 6. SYSTEM CONTROL BLOCK DIAGRAM
FIGURE 7. COMPENSATION REFERENCE CIRCUIT
13
FN9283.1
November 10, 2006
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