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| 型号： | ISL8118CRZ |
| 厂商： | Intersil |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 28-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 100% |
| 电源电压： | 2.97 V ~ 22 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 1244 (CN2011-ZH PDF) |
ISL8118
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
Margining Transfer Ratio
Positive Margining Threshold
Negative Margining Threshold
Tri-state Input Level
SYMBOL
N MARG
MARGIN
MARGIN
MARGIN
TEST CONDITIONS
N MARG = (V OFSN -V OFSP )/V MARG
Disable Mode
MIN
4.84
1.51
0.75
1.21
TYP
5
1.8
0.9
1.325
MAX
5.22
2.02
1.05
1.40
UNITS
SDR
V
V
V
NOTE:
3. Limits should be considered typical and are not production tested.
Functional Pin Descriptions
VSENSP (Pin 1)
This pin provides differential remote sense for the ISL8118. It
is the positive input of a standard instrumentation amplifier
topology with unity gain, and should connect to the positive
rail of the load/processor. The voltage at this pin should be
set equal to the internal system reference voltage (0.591V
typical).
VSENSN (Pin 2)
This pin provides differential remote sense for the regulator.
It is the negative input of the instrumentation amplifier, and
should connect to the negative rail of the load/processor.
Typically 6μA is sourced from this pin. The output of the
remote sense buffer is disabled (High Impedance) by pulling
VSENSN to VCC.
REFOUT (Pin 3)
This pin connects to the unmargined system reference
through an internal buffer. It has a 19mA drive capability with
an output common mode range of GND to VCC. The
REFOUT buffer requires at least 1μF of capacitive loading to
be stable. This pin should not be left floating.
REFIN (Pin 4)
When the external reference pin (REFIN) is NOT within
~800mV of VCC, the REFIN pin is used as the system
reference instead of the internal 0.591V reference. The
recommended REFIN input voltage range is ~60mV to
VCC - 1.8V.
SS (Pin 5)
This pin provides soft-start functionality for the ISL8118. A
capacitor connected to ground along with the internal 38μA
Operational Transconductance Amplifier (OTA), sets the soft-
start interval of the converter. This pin is directly connected to
the non-inverting input of the Error Amplifier. To prevent noise
injection into the error amplifier, the SS capacitor should be
located within 150 mils of the SS and GND pins.
OFSP (Pin 6)
This pin sets the positive margining offset voltage. Resistors
should be connected to GND (R OFSP ) and OFSN (R MARG )
from this pin. With MARGIN logic low, the internal 0.591V
9
reference is developed at the OFSP pin across resistor
R OFSP . The voltage on OFSP is driven from OFSN through
R MARG . The resulting voltage differential between OFSP and
OFSN is divided by 5 and imposed on the system reference.
The maximum designed offset of 1V between OFSP and
OFSN pins translates to a 200mV offset.
OFSN (Pin 7)
This pin sets the negative margining offset voltage. Resistors
should be connected to GND (R OFSN ) and OFSP (R MARG )
from this pin. With MARGIN logic low, the internal 0.591V
reference is developed at the OFSN pin across resistor
R OFSN . The voltage on OFSN is driven from OFSP through
R MARG . The resulting voltage differential between OFSP and
OFSN is divided by 5 and imposed on the system reference.
The maximum designed offset of -1V between OFSP and
OFSN pins translates to a -200mV offset of the system
reference.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL8118 analog circuitry. The
pin should be connected to a 2.9V to 5.6V bias through an
RC filter from PVCC to prevent noise injection into the
analog circuitry. This pin can be powered off the internal or
external linear regulator options.
MARGIN (Pin 9)
The MARGIN pin controls margining function, a logic high
enables positive margining, a logic low sets negative
margining, a high impedance disables margining.
PGDLY (Pin 10)
Provides the ability to delay the output of the PGOOD
assertion by connecting a capacitor from this pin to GND. A
0.1μF capacitor produces approximately a 5ms delay.
PGOOD (Pin 11)
Provides an open drain Power Good signal when the output
is within 9% of nominal output regulation point with 6%
hysteresis (15%/9%), and after soft-start is complete.
PGOOD monitors the VDIFF pin.
EN (Pin 12)
This pin is compared with an internal 0.50V reference and
enables the soft-start cycle. This pin also can be used for
FN6325.2
November 29, 2012
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