参数资料
型号: ISL8120CRZ-T
厂商: Intersil
文件页数: 24/35页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 22 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8120
VIN
FIRST PWM PULSE
SS Settling at VREF + 100mV
ISL8120
2-PHASE
EN/FF1
R UP
ISL8120
2-PHASE
EN/FF1
0.0V
VOUT
t SS = -------------
EN/FF2
EN/FF2
-100mV
1280
F SW
EN_HYS
? N
EN_HYS
PHASE
t SS_DLY ≈ ------------
R
UP
V
= ----------------------------------------------------------
I
R DOWN
384
F SW
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
FIGURE 7. SOFT-START WITH VOUT = 0V
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp .
Since the EN/FF pins are pulled down under fault conditions,
UV
FIRST PWM PULSE
SS Settling at VREF + 100mV
VOUT
the pull-up resistor (R UP ) should be scaled to sink no more
than 5mA current from EN/FF pin. Essentially, the EN/FF
pins cannot be directly connected to VCC.
Soft-start
-100mV
FIGURE 8. SOFT-START WITH VOUT = UV
The ISL8120 has two independent digital soft-start circuitry
with fixed 1280 switching cycles. The soft-start time is
inversely proportional to the switching frequency and is
determined by the 1280-cycle digital counter. Refer to
Figure 7. The full soft-start time from 0V to 0.6V can be
estimated using Equation 1.
FIRST PWM PULSE
OV = 113%
VOUT TARGET VOLTAGE
t SS = -------------
1280
f SW
(EQ. 1)
FIGURE 9. SOFT-START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
The ISL8120 has the ability to work under a pre-charged
output (see Figure 8). The output voltage would not be
Power-Good
CHANNEL 1 UV/OV
yanked down during pre-charged start-up. If the pre-charged
output voltage is greater than the final target level but prior to
113% setpoint, the switching will not start until the output
voltage reduces to the target voltage and the first PWM
pulse is generated (see Figure 9). The maximum allowable
pre-charged level is 113%. If the pre-charged level is above
CHANNEL 2 UV/OV
END OF SS1
OR
END OF SS2
SS1_PERIOD
AND
SS2_PERIOD
AND
PGOOD
113% but below 120%, the output will hiccup between 113%
(LGATE turns on) and 87% (LGATE turns off) while EN/FF is
pulled low. If the pre-charged load voltage is above 120% of
the targeted output voltage, then the controller will be
+20%
latched off and not be able to power-up.
For above-target level pre-charged start-up, the output
voltage would not change until the end of the soft-start. If the
initial dip is below the UV level, the LGATE could be turned
off. In such an event, the body-diode drop of the low-side
FET will be sensed and could potentiality cause an OCP
VMON1, 2
+13%
+9%
V REF
-9%
event for r DS(ON) current sensing applications.
PGOOD
-13%
PGOOD latch off after 120% OV
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
24
March 20, 2009
FN6641.0
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