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参数资料
| 型号： | ISL8501IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC REG TRPL BUCK/LINEAR 24QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）（1），线性（LDO）（2） |
| 功能： | 任何功能 |
| 输出数： | 3 |
| 频率 - 开关： | 500kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 0.6 V ~ 4.2 V，500mA |
| 电压/电流 - 输出 3： | 0.6 V ~ 4.2 V，500mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 6 V ~ 25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL8501
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
2. Place1st Zero Below Filter’s Double Pole (~75% f LC ).
3. Place 2nd Zero at Filter ’s Double Pole.
4. Place 1st Pole at the ESR Zero.
5. Place 2nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
-------------- × ? I OUT
+ ------ × ? ----------------------------- × -------------- ? ?
I RMS
?
V IN ? ?
?
L × f s
V IN
f Z1 = ------------------------------------
f Z2 = -------------------------------------------------------
f P1 = ---------------------------------------------------------
2 π x R 4 x ? ---------------------- ?
f P2 = ------------------------------------
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the Equation 6:
V OUT 2 1 V IN – V OUT V OUT 2
=
MAX MAX 12
1
2 π x R 4 x C 2
1
2 π x ( R 1 + R 3 ) x C 1
1
? C 3 x C 2 ?
? C 3 + C 2 ?
1
2 π x R 3 x C 1
(EQ. 8)
(EQ. 6)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised wih
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 2 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The error
Figure 3 shows an asymptotic plot of the DC/DC converter ’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 3. Using the guidelines from “Modulator
Break Frequency Equations” on page 17 should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at f P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 33 by adding the Modulator Gain (in dB)
to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
amplifier output (V E/A ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V IN at the PHASE node. The
OSC
PWM
COMPARATOR
DRIVER
V IN
L O
V DDQ
-
PWM wave is smoothed by the output filter (L O and C O ).
Δ V OSC
+
DRIVER
PHASE
C O
The modulator transfer function is the small-signal transfer
-
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at f LC and a zero at f ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
Modulator Break Frequency Equations
Z FB
V E/A
+
ERROR
AMP
Z IN
REFERENCE
ESR
(PARASITIC)
f LC = -------------------------------------------
f ESR = --------------------------------------------
V DDQ
Z IN
1
2 π x LO x CO
1
2 π x ESR x C O
(EQ. 7)
DETAILED COMPENSATION COMPONENTS
Z FB
C 3
The compensation network consists of the error amplifier
(internal to the ISL8501) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180°. The following equations relate the compensation
C 2
COMP
ISL8501
-
+
R 4
FB
C 1
R 2
R 1
R 3
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 4 , C 1 , C 2 , and C 3 ) in Figure 2. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
17
REFERENCE
FIGURE 32. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
FN6500.1
July 12, 2007
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