参数资料
| 型号： | ISL85033IRTZ |
| 厂商： | Intersil |
| 文件页数： | 21/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 28TQFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 28 V |
| 输入电压： | 4.5 V ~ 28 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-TQFN（4x4） |
ISL85033
Vo
Put the compensator zero at 6.6kHz (~1.5x C o R o ), and put the
compensator pole at ESR zero, which is 1.45MHz. The
R 2
R 3
C 3
V FB
V REF
-
+
GM
V COMP
R 1
C 2
compensator capacitors are:
C 1 = 470pF, C 2 = 3pF (There is approximately 3pF parasitic
capacitance from V COMP to GND; therefore, C 2 is optional).
Figure 48A shows the simulated voltage loop gain. It is shown
that it has 80kHz loop bandwidth with 69° phase margin and
15dB gain margin. Optional addition phase boost can be added
to the overall loop response by using C 3 .
C 1
60
45
FIGURE 47. TYPE II COMPENSATOR
Figure 47 shows the type II compensator and its transfer function
is expressed as Equation 23:
30
15
GAIN (dB)
? 1 + ------------ ? ? 1 + ------------ ?
ω cz1
ω cz2
g m
v ? comp
A v ( S ) = ---------------- = ------------------- ---------------------------------------------------------
C 1 + C 2
v ? FB
S 1 + ---------- ?
? ω ?
Where:
S S
? ? ? ?
? S
cp
(EQ. 23)
0
-15
-30
100
1?10 3
1?10 4
FIGURE 48A.
1?10 5
1?10 6
ω cz1 = -------------- , ω cz2 = -------------- , ω cp = ---------------------
R 1 C 1 R 2 C 3 R 1 C 1 C 2
the compensator design goal is:
High DC gain
1 1 C 1 + C 2
(EQ. 24)
100
80
Loop bandwidth f c : ? -- 4 - to ------- ? f s
Gain margin: >10dB
Phase margin: 40°
? 1 1 ?
10
60
40
20
PHASE (°)
(EQ. 25)
Put compensator zero ω cz1 = ( 1to3 ) ---------------
R C
The compensator design procedure is shown in Equation 25:
1
O O
Put one compensator pole at zero frequency to achieve high DC
0
-20
100
1?10 3
1?10 4
1?10 5
1?10 6
2 π f c V o C o R T
R 1 = ---------------------------------
(EQ. 27)
C 1 = ----------------- , C 2 = -------------------------
P D [ W ] = I OUT ? V D ? ? ?
? V OUT ? (EQ. 28)
V IN ?
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower.
The loop gain T v (S) at crossover frequency of f c has unity gain.
Therefore, the compensator resistance R 1 is determined by
Equation 26:
(EQ. 26)
g m V FB
where g m is the trans-conductance of the voltage error amplifier,
typically 200μA/V. Compensator capacitor C 1 is then given by
Equation 27:
1 1
R 1 ω cz 2 π R 1 f esr
Example: V IN = 12V, V o = 5V, I o = 3A, f s = 500kHz,
C o = 220μF/5m Ω , L = 5.6μH, g m = 200μs, R T = 0.21,
V FB = 0.8V, S e = 1.1 × 10 5 V/s, S n = 3.4 × 10 5 V/s, f c = 80kHz, then
compensator resistance R 1 = 72k Ω .
21
FIGURE 48B.
Rectifier Selection
Current circulates from ground to the junction of the external
Schottky diode and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is negative
with respect to ground. This voltage is approximately -0.5V (a
Schottky diode drop) during the off-time. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating factor.
The power dissipation when the Schottky diode conducts is
expressed in Equation 28:
1 – -------------
?
Where:
V D is the voltage drop of the Schottky diode. Selection of the
Schottky diode is critical in terms of the high temperature
reverse bias leakage current which is very dependent on VIN and
FN6676.6
February 23, 2012
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