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参数资料
| 型号： | ISL8540EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8540 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 5V |
| 电流 - 输出： | 2A |
| 输入电压： | 9 ~ 40 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8540 |
ISL8540
Δ V ESR = ESR ? I tran
Δ V ESL = ESL ? ---------------
L out ? I tran
Δ V SAG = --------------------------------------------------
Undervoltage Protection
If the voltage detected on the FB pin falls 14% below the
internal reference voltage and the overcurrent condition flag
is LOW, then the regulator will be shut down immediately
under an undervoltage fault condition. An undervoltage fault
condition will result with the regulator attempting to restart in
a hiccup mode with the delay between restarts being 4
soft-start periods. At the end of the fourth soft-start wait
period, the fault counters are reset and soft-start is
attempted again.
Thermal Protection
If the ISL8540 IC junction temperature reaches a nominal
temperature of +150°C, the regulator will be disabled. The
ISL8540 will not re-enable the regulator until the junction
temperature drops below +135°C.
Output Capacitor Selection
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
High frequency capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
During the removal of the same output load, the energy
stored in the inductor is dumped into the output capacitors.
This energy dumping creates a temporary hump in the
output voltage. This hump, as with the sag, can be attributed
to the total amount of capacitance on the output. Figure 27
shows a typical response to a load transient.
Δ V HUMP
V OUT
Δ V ESR
Δ V SAG
Δ V ESL
I OUT
I tran
FIGURE 27. TYPICAL TRANSIENT RESPONSE
The amplitudes of the different types of voltage excursions
can be approximated by using the formulas in Equation 4:
dI tran
dt
2
C out ? ( V in – V out )
L out ? I tran
C out ? V out
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
The shape of the output voltage waveform during a load
transient that represents the worst case loading conditions
will ultimately determine the number of output capacitors and
their type. When this load transient is applied to the
2
Δ V HUMP = --------------------------------
where
I tran = Output Load Current Transient
C out = Total Output Capacitance
(EQ. 4)
converter, most of the energy required by the load is initially
delivered from the output capacitors. This is due to the finite
amount of time required for the inductor current to slew up to
the level of the output current required by the load. This
phenomenon results in a temporary dip in the output voltage.
At the very edge of the transient, the Equivalent Series
Inductance (ESL) of each capacitor induces a spike that
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the
ESL are typically the major contributing factors in
determining the output capacitance. The number of output
capacitors can be determined by using Equation 5, which
relates the ESR and ESL of the capacitors to the transient
load step and the voltage limit ( Δ V O ):
--------------------------------- + ESR ? I tran
Number of Caps = -----------------------------------------------------------------------
adds on top of the existing voltage drop due to the
Equivalent Series Resistance (ESR).
After the initial spike, attributable to the ESR and ESL of the
ESL ? dI tran
dt
Δ V o
(EQ. 5)
capacitors, the output voltage experiences sag. This sag is a
direct consequence of the amount of capacitance on the
output.
12
If Δ V SAG and/or Δ V HUMP are found to be too large for the
output voltage limits, then the amount of capacitance may need
to be increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
FN6495.5
September 9, 2008
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