参数资料
| 型号： | ISL8540IVEZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 20HTSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.21 V ~ 35 V |
| 输入电压： | 9 V ~ 40 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 100kHz ~ 600kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-TSSOP-EP |
ISL8540
OSC
PWM
COMPARATOR
DRIVER
V IN
LX
L O
V OUT
1. Pick Gain (R 3 gm/(R 2 +R 3 ) for desired converter
bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% f LC ).
-
-
Δ V OSC
+
Z FB
V E/A
+
ERROR
AMP
DRIVER
Z IN
REFERENCE
C O
D
ESR
(PARASITIC)
3. Place 2 ND Zero at Filter ’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s Open-
Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency
DETAILED COMPENSATION COMPONENTS
Equations
f Z1 = ----------------------------------------------------------
2 π ? ---------------------------------- ? C 6
f Z2 = ---------------------------
f P1 = ---------------------------
f P2 = -----------------------------
C 10
C 6
COMP
R 4
Z FB
C 7
Z IN
R 2
R 6
V OUT
1
( R 4 ? g m + 1 )
g m
1
2 π R 2 ? C 7
1
2 π R 6 ? C 7
1
2 π R 4 ? C 10
(EQ. 12)
g m -
+
ISL8540
REFERENCE
FB
R 3
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 29 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 29. Using the guidelines in “Modulator Break
1 + ------ 2 -
V OUT = 1.20 × ? ?
? R ?
? R 3 ?
FIGURE 28. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at f LC and a zero at f ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC . The ISL8540
incorporates a feed forward loop that accounts for changes in
the input voltage. This maintains a constant modulator gain.
Modulator Break Frequency Equations
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 29 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
f LC = -------------------------------------------
f ESR = --------------------------------------------
1
2 π x LO x CO
1
2 π x ESR x C O
100
80
F Z1 F Z2
F P1
F P2
(EQ. 11)
The compensation network consists of the transconductance
60
OPEN LOOP
ERROR AMP GAIN
F ESR
amplifier (internal to the ISL8540) and the impedance
networks Z IN and Z FB . The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f 0dB ) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f 0dB and 180°. The equations in the following
section relate the compensation network’s poles, zeros and
gain to the components (R 2 , R 3 , R 4 , R 6 , C 10 , C 6 , and C 7 ) in
Figure 28. Use these guidelines for locating the poles and
zeros of the compensation network:
40
20
0
-20
-40
-60
20LOG
(R 4 /R 2 )
MODULATOR
GAIN
10 100
1k
20LOG
(V IN / Δ V OSC )
F LC
10k 100k 1M
FREQUENCY (Hz)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
FIGURE 29. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
14
FN6495.5
September 9, 2008
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