参数资料
型号: ISL8701IBZ-T
厂商: Intersil
文件页数: 4/13页
文件大小: 0K
描述: IC SEQUENCER QUAD ADJ 14-SOIC
标准包装: 2,500
类型: 序列发生器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 带卷 (TR)
ISL8700, ISL8701, ISL8702
Electrical Specifications
Nominal V IN = 2.5V to +24V, T A = T J = -40°C to +85°C, Unless Otherwise Specified.
ISL8702 V IN = 2.5V to +12V (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS
IC Supply Current
V IN Power On Reset
I VIN_2.2V
I VIN_12V
I VIN_24V
V IN_POR
V IN = 2.2V
V IN = 12V
V IN = 24V
V IN low to high
-
-
-
-
191
246
286
2.08
-
400
-
2.5
μA
μA
μA
V
Pin Descriptions
PIN NUMBER
ISL8700 ISL8701 ISL8702
PIN NAME
FUNCTION DESCRIPTION
NA
1
NA
ENABLE#_D
Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output to
sequence off for the ISL8701. Tracks V IN upon bias.
1
NA
1
ENABLE_D
Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to
sequence off for the ISL8700, ISL8702. Pulls low with V IN < 1V.
NA
2
NA
ENABLE#_C
Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced off after
ENABLE#_D for the ISL8701. Tracks V IN upon bias.
2
NA
2
ENABLE_C
Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced off after
ENABLE_D for the ISL8700, ISL8702. Pulls low with V IN < 1V.
NA
3
NA
ENABLE#_B
Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced off after
ENABLE#_C for the ISL8701. Tracks V IN upon bias.
3
NA
3
ENABLE_B
Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced off after
ENABLE_C for the ISL8700, ISL8702. Pulls low with V IN < 1V.
NA
4
NA
ENABLE#_A
Active low open drain sequenced output. Sequenced on after CTIME period and sequenced off after
ENABLE#_B for the ISL8701. Tracks V IN upon bias.
4
NA
4
ENABLE_A
Active high open drain sequenced output. Sequenced on after CTIME period and sequenced off after
ENABLE_B for the ISL8700, ISL8702. Pulls low with V IN < 1V.
5
5
5
OV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be immediately
pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull
ups.
6
6
6
UV
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be immediately
pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull
ups.
7
NA
7
NA
7
8
GND
FAULT
IC ground.
The V IN voltage when not within the desired UV to OV window will cause FAULT to be released to be
pulled high to a voltage equal to or less than V IN via an external resistor.
NA
NA
10
NA
NA
10
9
NA
10
SEQ_EN
SEQ_EN#
TIME
This pin provides a sequence on signal input with a high input. Internally pulled high to V IN .
This pin provides a sequence on signal input with a low input. Internally pulled high to V IN .
This pin provides a 2.6μA current output so that an adjustable V IN valid to sequencing on and off start
delay period is created with a capacitor to ground.
11
11
11
TB
A resistor connected from this pin to ground determines the time delay from ENABLE_A being active
to ENABLE _B being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
12
12
12
TC
A resistor connected from this pin to ground determines the time delay from ENABLE_B being active
to ENABLE _C being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
13
13
13
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_C being active
to ENABLE _D being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
14
14
14
V IN
IC Bias Pin Nominally 2.5V to 24V (2.5V to 12V for ISL8702) . This pin requires a 1μF decoupling
capacitor close to IC pin.
4
FN9250.2
March 21, 2008
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