参数资料
型号: ISL8701IBZ-T
厂商: Intersil
文件页数: 5/13页
文件大小: 0K
描述: IC SEQUENCER QUAD ADJ 14-SOIC
标准包装: 2,500
类型: 序列发生器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 带卷 (TR)
ISL8700, ISL8701, ISL8702
Functional Block Diagram
V IN (2.2V MIN TO 27V MAX, 2.5V TO 12V FOR ISL8702)
V IN
VREF
VOLTAGE
SEQ_EN
1.17V
REFERENCE
VREG INTERNAL VOLTAGE
3.5V
REGULATOR
UV
+
-
+
eo
LOGIC
2.0V VIN POR
ENABLE_A
OV
FAULT
-
30μs
ENABLE_B
ENABLE_C
GND
V TIME_VTH
VI N
PROGRAMMABLE
DELAY TIMER
ENABLE_D
2.6 μ A
TIME
TB
TC
TD
Functional Description
The ISL870x family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 2.5V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870x initiate the pre-programmed A-B-C-D sequence of the
ENABLE (ISL8700, ISL8702) or ENABLE# (ISL8701) outputs.
Although this IC has a bias range of 2.5V to 24V (12V for
ISL8702) it can monitor any voltage >1.22V via the external
divider if a suitable bias voltage is otherwise provided.
During initial bias voltage (V IN ) application, the ISL8700,
ISL8702 ENABLE outputs are held low once V IN = 1V whereas
the ISL8701 ENABLE# outputs follow the rising V IN . Once
V IN > the V BIAS power-on reset threshold (POR) of 2.0V, V IN
is constantly monitored for compliance via the input voltage
resistor divider and the voltages on the UV and OV pins and
reported by the FAULT output. Internally, voltage regulators
generate 3.5V and 1.17V ±5% voltage rails for internal usage
once V IN > POR. Once UV > 1.22V and with the SEQ_EN pin
high or open, the auto sequence of the four ENABLE
(ENABLE#) outputs begins as the TIME pin charges its external
capacitor with a 2.6μA current source. The voltage on TIME is
compared to the internal reference (V TIME_VTH ) comparator
input and when greater than V TIME_VTH the ISL8700, ISL8702
ENABLE_A is released to go high via an external pull-up
5
resistor or a pull-up in a DC/DC convertor enable input, for
example. Conversely, ENABLE#_A output will be pulled low at
this time on an ISL8701. The time delay generated by the
external capacitor is to assure continued voltage compliance
within the programmed limits, as during this time any OV or UV
condition will halt the start-up process. TIME capacitor is
discharged once V TIME_VTH is met.
Once ENABLE_A is active (either released high on the
ISL8700, ISL8702 or pulled low on the ISL8701), a counter is
started and using the resistor on TB as a timing component, a
delay is generated before ENABLE_B is activated. At this time,
the counter is restarted using the resistor on TC as its timing
component for a separate timed delay until ENABLE_C is
activated. This process is repeated for the resistor on TD to
complete the A-B-C-D sequencing order of the ENABLE or
ENABLE# outputs. At any time during sequencing if an OV or
UV event is registered, all four ENABLE outputs will
immediately return to their reset state; low for ISL8700,
ISL8702 and high for ISL8701. C TIME is immediately
discharged after initial ramp-up thus waiting for subsequent
voltage compliance to restart. Once sequencing is complete,
any subsequently registered UV or OV event will trigger an
immediate and simultaneous reset of all ENABLE or ENABLE#
outputs.
FN9250.2
March 21, 2008
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