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| 型号： | ISL8724IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/14页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY SEQUENCER 24QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 应用： | 电源序列发生器 |
| 电源电压： | 2.5 V ~ 5 V |
| 电流 - 电源： | 270µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
ISL8723, ISL8724
that are on a common connection thus unconditionally
shutting down all outputs across multiple sequencers. As
an input, if it is pulled low all GATEs will be unconditionally
shut off and RESET pulled low (see Figure 18). This pin
can also be used as a ‘no wait’ enabling input if all inputs
(ENABLE and UVLO) are satisfied; it does not wait through
delay to the start of GATE transition. There is no enable
lock out delay for a sequence off, so this table illustrates
the delay to GATE transition from a disable signal.
TABLE 1.
NOMINAL DELAY TO SEQUENCING THRESHOLD
the ~10ms enable delay to initiate the DLY_ON capacitor
charging when released to go high. This feature can be
used where 4 voltages can be monitored in addition to a
on-off switch position or, in the case of the ISL8724, a
present pin pull-down.
Restart of the turn on sequence is automatic once all
requirements are met. This allows for no interaction
between the sequencer and a controller IC if so desired.
If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground then all such related GATEs
DLY PIN
CAPACITANCE
Open
100pF
1000pF
0.01 μ F
0.1 μ F
1 μ F
TIME
(ms)
0.02
0.135
1.35
13.5
135
1350
start to turn on immediately after the 10ms (t UVLOdel )
ENABLE stabilization time out has expired and the GATEs
start to immediately turn off when ENABLE is deasserted.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.27V reference for various capacitor
values on the DLY_X pins. This table does not include the
10ms of enable lock out delay during a start-up sequence
but represents the time from the end of the enable lock out
l
NOTE: Nom. T DEL_SEQ = dly_cap (μF)x1.35M Ω
Figure 3 illustrates the turn-on and Figure 4 the nominal turnoff
timing diagrams of the ISL8723 and ISL8724 product.
Note the delay and flexible sequencing possibilities. Multiple
series, parallel or adjustable capacitors can be used to easily
fine tune timing between that offered by standard value
capacitors.
UVLO_A
V UVLOVth
V UVLOVth
<tFIL
UVLO_B
V UVLOVth
UVLO_C
UVLO_D
ENABLE (ISL8724)
ENABLE (ISL8723)
V UVLOVth
t UVLOdel
V EN
DLY_Vth
DLYON_B
DLY_Vth
DLYON_D
DLY_Vth
DLYON_A
DLYON_C
GATE_B
GATE_D
GATE_C
GATE_A
DLY_Vth
V QPUMP -1V
t RSTdel
V QPUMP
V QPUMP
V QPUMP
V QPUMP
RESET
SYSRST
FIGURE 3. ISL8723, ISL8724 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
6
FN6413.1
April 22, 2009
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