参数资料
型号: ISL8843MBZ
厂商: Intersil
文件页数: 8/12页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK ISO 8SOIC
标准包装: 980
PWM 型: 电流模式
输出数: 1
频率 - 最大: 2MHz
占空比: 100%
电源电压: 9 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -55°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
ISL8843
I OUT = Qg × f
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A . This GATE
output is actively held low when V DD is below the UVLO
threshold.
V DD - V DD is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
I DD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:
(EQ. 5)
To optimize noise immunity, bypass V DD to GND with a
ceramic capacitor as close to the V DD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1 μ F to 3.3 μ F capacitor to filter this output as
needed.
Functional Description
Features
The ISL8843 current mode PWM makes an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.
Oscillator
The ISL8843 has a sawtooth oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor from VREF and a capacitor to GND on the RTCT
pin. (Please refer to Figure 4 for the resistor and capacitance
required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method,
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft start is
complete. C1 continues to charge up to VREF and no longer
affects COMP. During power down, diode D1 quickly
discharges C1 so that the soft start circuit is properly
initialized prior to the next power on sequence.
Gate Drive
The ISL8843 is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
Fm = --------------------
illustrated below, clamps the voltage on COMP.
1
SnTsw
(EQ. 6)
where Sn is the slope of the sawtooth signal and Tsw is the
VREF
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
Fm = --------------------------------------- = ----------------------------
m c SnTsw
D1
R1
Q1
COMP
1 1
( Sn + Se ) Tsw
(EQ. 7)
m c = 1 + -------
C1
GND
where Se is slope of the external ramp and
Se
Sn
(EQ. 8)
The criteria for determining the correct amount of external
FIGURE 5. SOFT-START
8
ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching
FN9238.1
January 3, 2006
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ISL8843MBZ-T 功能描述:IC REG CTRLR BST FLYBK ISO 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL8843MUZ 功能描述:IC REG CTRLR BST FLYBK ISO 8MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL8843MUZ-T 功能描述:IC REG CTRLR BST FLYBK ISO 8MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ISL8844AABZ 功能描述:IC REG CTRLR BST FLYBK ISO 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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