参数资料
型号: ISL89160FBEBZ
厂商: Intersil
文件页数: 8/14页
文件大小: 0K
描述: IC MOSFET DRIVER 2CH 6A 8SOIC
标准包装: 980
配置: 低端
输入类型: 非反相
延迟时间: 25ns
电流 - 峰: 6A
配置数: 2
输出数: 2
电源电压: 4.5 V ~ 16 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-SOIC-EP
包装: 管件
ISL89160, ISL89161, ISL89162
Typical Performance Curves (Continued)
50
16V
1.1
V OUT LOW
40
NO LOAD
1.0
30
10V
0.9
V OUT HIGH
0.8
12V
20
10
5V
0.7
0.6
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.5
-45
-20
5
30
55
80
105
130
25
FREQUENCY (MHz)
FIGURE 12. I DD vs FREQUENCY (+25°C)
30
TEMPERATURE (°C)
FIGURE 13. r DS(ON) vs TEMPERATURE
FALL TIME, C LOAD = 10nF
OUTPUT FALLING PROP DELAY
25
OUTPUT RISING PROP DELAY
20
RISE TIME, C LOAD = 10nF
20
15
-45
-20
5
30 55 80
105
130
15
5
7
9
11
13
15
TEMPERATURE (°C)
FIGURE 14. OUTPUT RISE/FALL TIME
Functional Description
Overview
The ISL89160, ISL89161, ISL89162 drivers incorporate several
features including precision input logic thresholds, undervoltage
lock-out, and fast rising high output drive currents.
The precision input thresholds facilitate the use of an external RC
network to delay the rising or falling propagation of the driver
output. This is a useful feature to create dead times for bridge
applications to prevent shoot through.
The fast rising (or falling) output drive currents of the ISL89160,
ISL89161, ISL89162 minimize the turn-on (off) delays due to the
input capacitance of the driven FET. The switching transition period
at the Miller plateau is also minimized by high drive currents even
at these lower output voltages. (See the specified Miller plateau
currents in “AC Electrical Specifications” on page 5).
The start-up sequence is designed to prevent unexpected glitches
when V DD is being turned on or turned off. When V DD < ~1V, an
internal 10k ? resistor connected between the output and
8
V DD
FIGURE 15. PROPAGATION DELAY vs V DD
ground, help to keep the gate voltage close to ground. When
~1V < V DD < UV, both outputs are driven low while ignoring the
logic inputs. This low state has the same current sinking capacity
as during normal operation. This insures that the driven FETs are
held off even if there is a switching voltage on the drains that can
inject charge into the gates via the Miller capacitance. When
V DD > UVLO, and after a 400μs delay, the outputs now respond
to the logic inputs. See Figure 9 for complete details.
For the negative transition of V DD through the UV lockout voltage,
the outputs are active low when V DD < ~3.2V DC regardless of the
input logic states.
Application Information
Precision Thresholds for Time Delays
For input logic voltage option A, the nominal input negative
transition threshold is 1.22V and the positive transition threshold
is 2.08V (37% and 63% of 3.3V) Likewise, for input logic option B,
the nominal input negative transition threshold is 1.85V and the
positive transition threshold is 3.15V (37% and 63% of 4.0V).
FN7719.3
February 20, 2013
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