参数资料
型号: ISL9109IRZ-T
厂商: Intersil
文件页数: 11/13页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.5A 8DFN
标准包装: 6,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.6MHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(2x3)
ISL9109
Applications Information
V IN
STBY
EN
BAND-GAP
V OUT
400μS~1ms 1ms
BAND-GAP WAKE-UP WAIT
30μs
25μs V OUT
BIAS UP SOFT_START
25μs
BIAS UP
30μs
V OUT SOFT-START
BAND-GAP OFF @
EN=STBY=Low
400~800μs
BAND-GAP
WAKE-UP
25μs
BIAS UP
400~800μs
V OUT SOFT-START
FIGURE 23. TIMING DIAGRAM
Inductor and Output Capacitor Selection
To achieve better steady state and transient response, typically
a 2.2μH inductor can be used. The peak-to-peak inductor
current ripple can be expressed as follows in Equation 1:
Input Capacitor Selection
The main function for the input capacitor is to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
V O ? ? 1 – --------- ?
L ? f S
? V O ?
? V IN ?
Δ I = ---------------------------------------
(EQ. 1)
the battery rail. A 10μF/6.3V ceramic capacitor (X5R or X7R)
is a good starting point for the input capacitor selection.
Output Voltage Setting Resistor Selection
In Equation 1, usually the typical values can be used but to
have a more conservative estimation; the inductance should
consider the value with worst case tolerance. For switching
The voltage divider resistors, R 1 and R 2 , (as shown in
Figure 19), set the desired output voltage value. The output
voltage can be calculated using Equation 2:
V O = V FB ? ? 1 + ------- ?
frequency f S , the minimum f S from the “Electrical
Specifications” table on page 2 can be used.
To select the inductor, its saturation current rating should be at
? R 1 ?
? R 2 ?
(EQ. 2)
least higher than the sum of the maximum output current and
half of the delta calculated from Equation 1. Another more
conservative approach is to select the inductor with the current
rating higher than the P-Channel MOSFET peak current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered
to achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
Where V FB is the feedback voltage (typically it is 0.8V). The
current flowing through the voltage divider resistors can be
calculated as V O /(R 1 + R 2 ), so larger resistance is desirable
to minimize this current. On the other hand, the FB pin has
leakage current that will cause error in the output voltage
setting. The leakage current has a typical value of 0.1μA. To
minimize the accuracy impact on the output voltage, select
the R 2 no larger than 200k Ω .
C3 (shown in Figure 19) is highly recommended to be added
for improving stability, and achieving better transient
response. C3 should be 120pF or less to meet the 60μs
maximum soft-startup time when STBY = 1.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 10μF/6.3V ceramic
capacitor should be enough for most of the applications and
the capacitor should be X5R or X7R.
11
Table 1 provides the recommended component values for
some output voltage options.
FN6681.1
September 29, 2008
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