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| 型号： | ISL95810UIU8-T |
| 厂商： | INTERSIL CORP |
| 元件分类： | 数字电位计 |
| 英文描述： | Single Digitally Controlled Potentiometer (XDCP) |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封装： | PLASTIC, MO-187AA, MSOP-8 |
| 文件页数： | 13/13页 |
| 文件大小： | 1124K |
| 代理商： | ISL95810UIU8-T |
9
FN8090.2
September 19, 2006
The ISL95810 is pre-programed with 80h in the IVR.
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The ISL95810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95810
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL95810 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95810 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power-
up sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The ISL95810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (See Table 2).
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2-
Access Control
1
Reserved
0IVR
WR
TABLE 2. IDENTIFICATION BYTE FORMAT
0
1
0
1000
R/W
(MSB)
(LSB)
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
ISL95810
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