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参数资料
| 型号： | ISL95810UIU8-T |
| 厂商： | INTERSIL CORP |
| 元件分类： | 数字电位计 |
| 英文描述： | Single Digitally Controlled Potentiometer (XDCP) |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封装： | PLASTIC, MO-187AA, MSOP-8 |
| 文件页数： | 8/13页 |
| 文件大小： | 1124K |
| 代理商： | ISL95810UIU8-T |
4
FN8090.2
September 19, 2006
ILkgDig
Leakage Current, at Pins SDA, SCL,
and WP Pins
Voltage at pin from GND to VCC
-10
10
A
tDCP (Note 13)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1s
Vpor
Power-On Recall Voltage
Minimum VCC at which memory recall occurs
1.8
2.6
V
VCCRamp
VCC Ramp Rate
0.2
V/ms
tD (Note 13)
Power-Up Delay
VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in standby state
3ms
EEPROM SPECIFICATIONS
EEPROM Endurance
200,000
Cycles
EEPROM Retention
Temperature
≤ +75°C
50
Years
SERIAL INTERFACE SPECIFICATIONS
VIL
WP, SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC
V
VIH
WP, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC+0.3
V
Hysteresis (Note 13) SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL (Note 13)
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin (Note 13)
WP, SDA, and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN (Note 13)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA (Note 13)
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
900
ns
tBUF (Note 13)
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STO:NV
STOP Condition Hold Time for Non-
Volatile Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
2s
tDH (Note 13)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
0ns
tR (Note 13)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 13)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 13)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ISL95810
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