参数资料
| 型号： | ISL95870BIRZ |
| 厂商： | Intersil |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 1PHASE GPU 20QFN |
| 标准包装： | 75 |
| 应用： | 控制器，GPU 内核电源 |
| 输入电压： | 3.3 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（3x4） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
ISL95870, ISL95870A, ISL95870B
V SREF ? C SOFT
t SS = -------------------------------------------
t SS = – ( R T ? C SOFT ) ? LN ( 1 – ------------------------------ )
V START-UP
I SS ? R T
t SS ? I SS
C SOFT = -----------------------
t VS = – ( R T ? C SOFT ) ? LN ( 1 – ------------------------------------------- )
( V NEW – V OLD )
I VS ? R T
Theory of Operation
The following sections will provide a detailed description of the
inner workings of the ISL95870, ISL95870A, ISL95870B.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has increased
above the rising power-on reset (POR) threshold voltage
V VCC_THR . The controller will become disabled when the voltage
at the VCC pin decreases below the falling POR threshold voltage
V VCC_THF . The POR detector has a noise filter of approximately
1μs.
Start-Up Timing
Once VCC has ramped above V VCC_THR , the controller can be
enabled by pulling the EN pin voltage above the input-high
threshold V ENTHR . Approximately 20μs later, the voltage at the
SREF pin begins slewing to the designated VID set-point. The
converter output voltage at the FB feedback pin follows the
voltage at the SREF pin. During soft-start, The regulator always
operates in CCM until the soft-start sequence is complete.
Start-Up and Voltage-Step Operation for
ISL95870
When the voltage on the VCC pin has ramped above the rising
power-on reset voltage V VCC_THR , and the voltage on the EN pin
has increased above the rising enable threshold voltage V ENTHR ,
the SREF pin releases its discharge clamp, and enables the
reference amplifier V SET . The soft-start current I SS is limited to
17μA and is sourced out of the SREF pin and charges capacitor
C SOFT until V SREF equals V REF . The regulator controls the PWM
such that the voltage on the FB pin tracks the rising voltage on
the SREF pin. The elapsed time from when the EN pin is asserted
to when V SREF has charged C SOFT to V REF is called the soft-start
delay t SS which is given by Equation 1:
(EQ. 1)
I SS
Where:
- I SS is the soft-start current source at the 17μA limit
- V SREF is the buffered V REF reference voltage
The end of soft-start is detected by I SS tapering off when
capacitor C SOFT charges to V REF . The internal SSOK flag is set,
the PGOOD pin goes high, and diode emulation mode (DEM) is
enabled.
Choosing the C SOFT capacitor to meet the requirements of a
particular soft-start delay t SS is calculated using Equation 2,
which is written as follows:
(EQ. 2)
V SREF
Where:
- t SS is the soft-start delay
- I SS is the soft-start current source at the 17μA limit
- V SREF is the buffered V REF reference voltage
Choosing the C SOFT capacitor to meet the requirements of a
particular soft-start delay t SS is calculated with Equation 6,
15
Start-Up and Voltage-Step Operation for
ISL95870A, ISL95870B
When the voltage on the VCC pin has ramped above the rising
power-on reset voltage V VCC_THR , and the voltage on the EN pin
has increased above the rising enable threshold voltage V ENTHR ,
the SREF pin releases its discharge clamp and enables the
reference amplifier V SET . The soft-start current I SS is limited to
17μA and is sourced out of the SREF pin into the parallel RC
network of capacitor C SOFT and resistance R T . The resistance R T
is the sum of all the series connected R SET programming
resistors and is written as Equation 3:
R T = R SET1 + R SET2 + … R SET ( n ) (EQ. 3)
The voltage on the SREF pin rises as I SS charges C SOFT to the
voltage reference setpoint selected by the state of the VID inputs at
the time the EN pin is asserted. The regulator controls the PWM
such that the voltage on the FB pin tracks the rising voltage on the
SREF pin. Once C SOFT charges to the selected setpoint voltage, the
I SS current source comes out of the 17μA current limit and decays
to the static value set by V SREF /R T . The elapsed time from when the
EN pin is asserted to when V SREF has reached the voltage reference
setpoint is the soft-start delay t SS which is given by Equation 4:
(EQ. 4)
Where:
- I SS is the soft-start current source at the 17μA limit
- V START-UP is the setpoint reference voltage selected by the
state of the VID inputs at the time EN is asserted
- R T is the sum of the R SET programming resistors
The end of soft-start is detected by I SS tapering off when
capacitor C SOFT charges to the designated V SET voltage
reference setpoint. The SSOK flag is set, and the PGOOD pin goes
high.
The I SS current source changes over to the voltage-step current
source I VS which has a current limit of ±85μA. Whenever the VID
inputs or the external setpoint reference programs a different
setpoint reference voltage, the I VS current source charges or
discharges capacitor C SOFT to that new level at ±85μA. Once
C SOFT charges to the selected setpoint voltage, the I VS current
source comes out of the 85μA current limit and decays to the
static value set by V SREF /R T . The elapsed time to charge C SOFT
to the new voltage is called the voltage-step delay t VS and is
given by Equation 5:
(EQ. 5)
Where:
- I VS is the ±85μA setpoint voltage-step current; positive
when V NEW > V OLD , negative when V NEW < V OLD
- V NEW is the new setpoint voltage selected by the VID inputs
- V OLD is the setpoint voltage that V NEW is changing from
- R T is the sum of the R SET programming resistors
FN6899.1
December 2, 2013
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