参数资料
型号: ISL97635IRZ-T
厂商: Intersil
文件页数: 16/28页
文件大小: 0K
描述: IC LED DRVR WHT/RGB BCKLGT 24QFN
标准包装: 6,000
拓扑: PWM,升压(升压)
输出数: 8
内部驱动器:
类型 - 主要: 车载,背光
类型 - 次要: RGB,白色 LED
频率: 600kHz,1.2MHz
电源电压: 6 V ~ 24 V
输出电压: 34.5V
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
ISL97635
TABLE 1. PROTECTIONS TABLE
VOUT
CASE
1
FAILURE MODE
CH0 Short Circuit
DETECTION MODE
Upper
FAILED CHANNEL ACTION
CH0 ON and burns power
GOOD CHANNELS ACTION
CH1 through CH7 Normal
REGULATED BY
Highest VF of
Over-Temperature
Protection limit (OTP)
not triggered and VIIN0
< VSC
CH1 through CH7
2
CH0 Short Circuit
Upper OTP triggered but CH0 goes off until chip cooled and
VIN0 < VSC
then comes back on with current
Same as CH0
Highest VF of
CH1 through CH7
reduced to 76%. Further OTP
triggers result in reduction to 53%,
then 30%. Thermal event reported
in Fault/Status Register.
3
CH0 Short Circuit
Upper OTP not triggered CH0 doubled after 6ms time-out.
but VIIN0 > VSC
Time-out reduced to 420μs if above
CH1 through CH7 Normal
Highest VF of
CH1 through CH7
lower OTP limit
4
CH0 Open Circuit
with infinite
Upper OTP not triggered V OUT will ramp to OVP. CH0 will
and VIIN0 < VSC
time-out after 6ms (800μs if above
CH1 through CH7 Normal
Highest VF of
CH1 through CH7
resistance
lower OTP limit) and switch off.
V OUT will drop to normal level.
5
CH0 LED Open
Circuit but has
Upper OTP not triggered CH0 remains ON and has highest
and VIIN0 < VSC
VF, thus V OUT increases
CH1 through CH7 ON, Q1
through Q7 burn power
VF of CH0
paralleled Zener
6
CH0 LED Open
Circuit but has
Upper OTP triggered but CH0 goes off until chip cooled and
VIIN0 < VSC
then comes back on with current
Same as CH0
VF of CH0
paralleled Zener
reduced to 76%. Further OTP
triggers result in reduction to 53%,
then 30%. Thermal event reported
in Fault/Status Register.
7
CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered CH0 OFF
but VIIN0 > VSC
Upper OTP not triggered CH0 remains ON and has highest
but VIINx > VSC
VF, thus V OUT increases.
CH1 through CH7 Normal
V OUT increases then CH-X
switches OFF. This is an
Highest VF of
CH1 through CH7
VF of CH0
unwanted shut off and can be
prevented by setting OVP and/or
VSC at an appropriate level.
8
Channel-to-Channel Lower OTP triggered but Any channel at below 50% of the target current will fault out after
Highest VF of
Δ VF too high
VIINx < VSC
400μs.
CH0 through CH7
Remaining channels driven with normal current.
9
Channel-to-Channel Upper OTP triggered but All channels switched off until chip cooled and then comes back on
Highest VF of
Δ VF too high
VIINx < VSC
with current reduced to 76%. Further OTP triggers result in reduction
CH0 through CH7
to 53%, then 30%. Thermal event reported in Fault/Status Register.
10
Output LED stack
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that is below 50% of the target Highest VF of
current will time-out after 6ms.
CH0 through CH7
11
VOUT/LX shorted to LX current and timing
Fault switch disabled and system shutdown until fault goes away,
GND
are monitored.
V OUT is checked at start-up with a low current from LX to check for
presence of short before the fault switch is enabled.
OVP pin monitored for
excursions below 20% of
OVP threshold
16
FN6434.2
December 22, 2008
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