参数资料
型号: ISL97650ARTZ-TK
厂商: Intersil
文件页数: 16/20页
文件大小: 0K
描述: IC LCD SUPPLY HP 4CHAN 36-TQFN
标准包装: 1
应用: LCD 电视机/监控器
电流 - 电源: 250µA
电源电压: 4 V ~ 14 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 标准包装
产品目录页面: 1249 (CN2011-ZH PDF)
其它名称: ISL97650ARTZ-TKDKR
ISL97650
V REF
C19
A2
VDD
VSUP
100pF
FAULT
0.4V
FBN
C20
820pF
R6
40k
A1
0.2V
R7
328k
1.2MHz
STOP
M2
CLK
NOUT
C12
220nF
D2
V OFF (-8V)
D3
C13
470nF
EN
PWM
CONTROL
M1
PGND
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
The maximum V OFF output voltage of a single stage charge pump is:
V OFF_MAX ( 2x ) = – V SUP + V DIODE + 2 ? I OUT ? ( r ON ( NOUT ) H + r ON ( NOUT ) L )
(EQ. 20)
determine V OFF output voltage.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as shown in
V OFF = V FBN ? ? 1 + -------- ? – V REF ? ? -------- ?
Δ V V g
( R i || R L ) × C L
Δ t
R7 R7
? R6 ? ? R6 ?
(EQ. 21)
Equation 22:
-------- = -------------------------------------
(EQ. 22)
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the Application
Diagram, C21 and C22 for the positive charge pump). Set
R6 ? C20 = R7 ? C19 with C19 ~ 100pF.
V ON Slice Circuit
Where V g is the supply voltage applied to DRN or voltage at
P OUT , which range from 0V to 36V. R i is the resistance
between COM and DRN or P OUT including the internal
MOSFET r DS(On) , the trace resistance and the resistor
inserted, R L is the load resistance of switch control circuit,
and C L is the load capacitance of switch control circuit.
In the “Typical Application Diagram” on page 10, R10, R11
and C15 give the bias to DRN based on Equation 23:
V DRN = ---------------------------------------------------------------
The V ON Slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and SRC,
under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30 Ω internal MOSFET, and if CTL is high,
COM connects to P OUT internally via a 5 Ω MOSFET.
16
V ON ? R 11 +AVDD ? R 10
R 10 + R 11
R12 can be adjusted to adjust the slew rate.
(EQ. 23)
FN9198.4
April 17, 2009
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