参数资料
型号: ISL97653AIRZ
厂商: Intersil
文件页数: 16/18页
文件大小: 0K
描述: IC LCD SUPPLY 5CHN 40-QFN
标准包装: 50
应用: LCD 电视机/监控器
电流 - 电源: 4mA
电源电压: 4 V ~ 14 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN 裸露焊盘(6x6)
包装: 管件
ISL97653A
FAULT
A2
0.4V
VDD
SUPN
FBN
C20
820pF
V REF
R6
40k
C19
100pF
A1
0.2V
R7
328k
1.2MHz
STOP
M2
CLK
NOUT
C12
220nF
D2
V OFF (-8V)
EN
PWM
CONTROL
M1
D3
C13
470nF
PGND
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
Δ V V g
(EQ. 20)
|| R ) × C
Δ t
( R i
A VDD = --------------------- × V FBB
R x
V ON Slice Circuit
The V ON slice circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and
POUT, under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is pulled to ground via
an NDMOS FET with r DS(ON) of 260 ? . After the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30 Ω internal MOSFET, and if CTL is high,
COM connects to P OUT internally via a 5 Ω MOSFET.
The slew rate of the switch control circuit is mainly restricted
by the load capacitance at COM pin and is given by
Equation 20:
-------- = -------------------------------------
L L
Where V g is the supply voltage applied to DRN or voltage at
P OUT , which range is from 0V to 30V. R i is the resistance
between COM and DRN or P OUT including the internal
MOSFET r DS(on) , the trace resistance and the resistor
inserted, R L is the load resistance of VON slice circuit, and
C L is the load capacitance of switch control circuit.
In the Typical Application Circuit, R 8 , R 9 and C 22 give the
bias to DRN based on Equation 21:
V LOGIC2 LDO
An LDO controller is also integrated to provide a second
logic supply. The LDO-CTL pin drives the base of an
external transistor which should be sized for the current
required. A resistor divider is used to set the output voltage
by feeding back a reference voltage to LDO-FB. The internal
feedback reference is 1.215V.
HVS Operation
When the HVS input is taken high, the ISL97653A enters
HVS test mode. In this mode, the output of A VDD is
increased by switching RSET to ground, and the AVDD is
set to:
R 3 + R x
(EQ. 22)
Where R x is the value of R 4 in parallel with R 5 . AVDD
voltage higher than the maximum rating of the boost
MOSFET may damage the part.
Fault Protection
The ISL97653A incorporates a number of fault protection
schemes. AVDD, VON, and VOFF are constantly monitored.
If fault conditions are detected for longer than 1ms on these
FB inputs, the device stops switching and the outputs are
disconnected. The ISL97653A also integrates over-temp
R 9 + R
V ON ? R 9 +AVDD ? R 8
V DRN = ---------------------------------------------------------
8
And R 10 can be adjusted to adjust the slew rate.
16
(EQ. 21)
and over current protection.
Supply Sequencing
When the input voltage V IN is higher than 4V(UVLO), V REF ,
V LOGIC, and V LOGIC2 are turned on. V LOGIC has a 9ms
fixed soft-start at start-up. A VDD , V ON , and V OFF are
dependant on the EN pin.
FN6367.3
September 7, 2010
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