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参数资料
| 型号： | ISL97677IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 17/23页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR PWM CTRL 8CH 32QFN |
| 标准包装： | 1,000 |
| 拓扑： | 线性（LDO），PWM，升压（升压） |
| 输出数： | 8 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 500kHz ~ 1.5MHz |
| 电源电压： | 4.75 V ~ 26 V |
| 输出电压： | 45V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
ISL97677
Write Byte
The Write Byte protocol is only three bytes long. The first
byte starts with the slave address followed by the
“command code,” which translates to the “register index”
being written. The third byte contains the data byte that
must be written into the register selected by the
“command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives”
confusion. Therefore, if the device is in the write mode
where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0
is 1, the slave address byte is 0x59 or 01011001b.
The backlight controller may sense the state of the pins
at POR or during normal operation—the pins will not
change state while the device is in operation.
the Data line. All other cycles are driven by the “host
master.”
MSB
LSB
Read Byte
0
1
0
1
1
0
0
R/ W
As shown in the Figure 28, the four byte long Read Byte
protocol starts out with the slave address followed by
the “command code” which translates to the “register
index.” Subsequently, the bus direction turns around
with the rebroadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That
DEVICE
IDENTIFIER
DEVICE
ADDRESS
byte value in the data byte reflects the value of the
register being queried at the “command code” index.
Note the bus directions, which are highlighted by the
shaded label that is used on cycles during which the
slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W
bit, but these 8 bits are usually called Slave Address
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
SMBus Register Definitions
The backlight controller registers are Byte wide and
accessible via the SMBus Read/Write Byte protocols.
Their bit assignments are provided in the following
sections with reserved bits containing a default value
of “0”.
bytes. As shown in Figure 29, the high nibble of the slave
address byte is 0x5 or 0101b to denote the “backlight
controller class.” Bit 3 in the lower nibble of the slave
address byte is 1. Bit 0 is always the R/W bit, as specified
by the SMBus protocol. Note: In this document, the
device address will always be expressed as a full 8-bit
address instead of the shorter 7-bit address typically
used in other backlight controller specifications to avoid
TABLE 2A. REGISTER LISTING
ADDRESS
0x00
0x01
REGISTER
PWM Brightness
Control Register
Device Control
Register
BIT 7
BRT7
Reserved
BIT 6
BRT6
Reserved
BIT 5
BRT5
Reserved
BIT 4
BRT4
Reserved
BIT 3
BRT3
Reserved
BIT 2
BRT2
PWM_MD
BIT 1
BRT1
PWM_SEL
BIT 0
BRT0
BL_CTL
DEFAULT
VALUE
0xFF
0x00
SMBUS
PROTOCOL
Read and Write
Read and Write
0x02
Fault/Status
Register
Reserved
Reserved
2_CH_SD
1_CH_S
D
BL_STAT
OV_CURR THRM_SHDN
FAULT
0x00
Read Only
0x03
Identification
Register
LED
PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
0xC8
Read Only
17
FN6996.1
November 13, 2009
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