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| 型号： | ISL97677IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 18/23页 |
| 文件大小： | 0K |
| 描述： | IC LED DVR PWM CTRL 8CH 32QFN |
| 标准包装： | 1,000 |
| 拓扑： | 线性（LDO），PWM，升压（升压） |
| 输出数： | 8 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 500kHz ~ 1.5MHz |
| 电源电压： | 4.75 V ~ 26 V |
| 输出电压： | 45V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
ISL97677
TABLE 2B. DATA BIT DESCRIPTIONS
ADDRESS
0x00
0x01
REGISTER
PWM Brightness Control
Register
Device Control Register
DATA BIT DESCRIPTIONS
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change),
default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by
SMBus), default = 0
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
PWM_MD PWM_SEL
MODE
X
1
0
1
0
0
PWMI Mode
SMBus Mode
SMBus and PWMI mode with
DPST
0x02
0x03
Fault/Status Register
Identification Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM
duty cycle adjustment. The bit assignment is shown in
Tables 2A and 2B. All of the bits in this Brightness Control
Register can be read or write. Step 0 corresponds to the
minimum step where the current is less than 10μA.
unless otherwise written. Bits 7 and 6 are not
implemented and will always read low.
TABLE 3. OPERATING MODES SELECTED BY DEVICE
CONTROL REGISTER BITS 1 AND 2
PWM_MD PWM_SEL MODE
Steps 1 to 255 represent the linear steps between 0.39%
and 100% duty cycle with approximately 0.39% duty
cycle adjustment per step.
? An SMBus Write Byte cycle to Register 0x00 sets the
X
1
0
1
0
0
PWMI Mode
SMBus Mode
SMBus and PWMI Mode with DPST
PWM brightness level only if the backlight controller
is in SMBus mode (see Table 3 “Operating Modes
selected by Device Control Register Bits 1 and 2”).
? An SMBus Read Byte cycle to Register 0x00 returns
the programmed PWM brightness level, regardless of
the value of PWM_SEL.
? An SMBus setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
? An SMBus setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness
output in which the LED current is guaranteed to be
less than 10μA.
The PWM_SEL bit determines whether the SMBus or
PWMI input should drive the output brightness in terms
of PWM dimming. When PWM_SEL bit is 1, the PWMI
drives the output brightness regardless of what the
PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted;
when this bit is 1, the PWM dimming is based on the
SMBus brightness setting. When this bit is 0, the PWM
dimming reflects a percentage change in the current
brightness programmed in the SMBus Register 0x00, i.e.
DPST (Display Power Saving Technology) mode, as
shown in Equation 6:
? Default value for Register 0x00 is 0xFF.
DPST Brightness = Cbt × PWMI
(EQ. 6)
Device Control Register (0x01)
This register has 2 bits that control the operating mode
of the backlight controller and a single bit that controls
the BL ON/OFF state. The remaining bits are reserved.
The bit assignment is shown in Tables 2A and 2B. All
other bits in the Device Control Register will read as low
18
Where:
Cbt = Current brightness setting from SMBus Register
0x00 without influence from the PWMI
PWMI = is the percent duty cycle of the PWMI
FN6996.1
November 13, 2009
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