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参数资料
| 型号： | ISP1583ET2 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64 |
| 文件页数： | 37/100页 |
| 文件大小： | 508K |
| 代理商： | ISP1583ET2 |
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ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
40 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.3.3 Data Port register (address: 20h)
This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed
endpoint. The bit allocation is shown in Table 39.
Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto
incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in
the TX FIFO. When all bytes are written (FIFO byte count = endpoint MaxPacketSize), the
Table 38.
Control Function register: bit description
Bit
Symbol
Description
7 to 5 -
reserved.
4
CLBUF
Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The
RX buffer is automatically cleared once the endpoint is completely read. This bit
is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the CLBUF
command two times. For details on clearing buffers, refer to Ref. 5 “ISP1582/83
3
VENDP
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to
send on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set
only when it is necessary to validate the endpoint with the FIFO byte count,
which is below endpoint MaxPacketSize.
Remark: Use either bit VENDP or register Buffer Length to validate endpoint
FIFO with FIFO bytes.
2
DSEN
Data Stage Enable: This bit controls the response of the ISP1583 to a control
transfer. After the completion of the set-up stage, rmware must determine
whether a data stage is required. For control OUT, rmware will set this bit and
the ISP1583 goes into the data stage. Otherwise, the ISP1583 will NAK the data
stage transfer. For control IN, rmware will set this bit before writing data to the
TX FIFO and validate the endpoint. If no data stage is required, rmware can
immediately set the STATUS bit after the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the
device and the IN token is acknowledged by the PC host. This bit cannot be
read back and reading this bit will return logic 0.
1
STATUS
Status Acknowledge: Only applicable for control IN or OUT.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is completed,
or when a SETUP token is received. No interrupt signal will be generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK
following the OUT token (host-to-peripheral)
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
Remark: Data transfers preceding the status stage must rst be fully completed
before the STATUS bit can be set.
0
STALL
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for
isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the
stalled endpoint because the internal logic picks up from where it is stalled.
Therefore, the Data Toggle bit must be reset by disabling and re-enabling the
corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in
the Endpoint Type register) to reset the PID.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISP1583ET2,518 | 功能描述:外围驱动器与原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| ISP1583ET2-T | 功能描述:外围驱动器与原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| ISP1583ET-T | 功能描述:外围驱动器与原件 - PCI HI-SPEED USB2 DEVICE RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| ISP1583ETUM | 功能描述:IC USB CTRL HI-SPEED 64TFBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| ISP166 | 功能描述:机架和机柜配件 PANELS 1600HX600D RoHS:否 制造商:Bivar 产品:Rack Accessories 面板空间: 颜色:Black |
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