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参数资料
| 型号： | ISPLSI 2192VE-135LB144 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 7.5NS 144FPBGA |
| 标准包装： | 160 |
| 系列： | ispLSI® 2000VE |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 48 |
| 宏单元数： | 192 |
| 门数： | 8000 |
| 输入/输出数： | 96 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-FPBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | ISPLSI2192VE-135LB144 |
Specifications ispLSI 2192VE
11
RESET
15
G4
GOE 0, GOE 1
80, 17
F12, G2
Y0, Y1, Y2
14, 83, 78
F3, F10, G11
BSCAN
19
F1
TDI/IN 0
20
G3
TMS/IN 1
48
J6
TDO/IN 6
112
C7
TCK/IN 7
77
G12
IN 2-5, IN 8-11
—, 49, 82, —, 84, 113, 13, —
M7, J7, F9, G10, E12, B6,
F2, E1
GND
18, 34, 50, 63, 79, 98, 111,
A1, A12, D4, D9, E5, E8, F6,
127
F7, G6, G7, H5, H8, J4, J9,
M1, M12
VCC
2, 16, 31, 47, 66, 81, 95, 114
B1, B12, E6, E7, F5, F8, G5,
G8, H6, H7, L1, L12
NC1
—K2
Signal Descriptions
RESET
Active Low (0) Reset pin resets all the registers in the device.
GOE 0, GOE1
Global Output Enable input pins.
Y0, Y1, Y2
Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a serial data input pin
to load programming data into the device. When
BSCAN is high, it functions as a dedicated input pin.
TCK/IN 7
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
TMS/IN 1
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
TDO/IN 6
Output/Input – This pin performs two functions. When
BSCAN is logic low, it functions as an output pin
to read serial shift register data. When
BSCAN is high, it functions as a dedicated input pin.
IN 2-5, IN 8-11
Dedicated Input Pins to the device.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
Signal Name
Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
Signal Name
128-Pin TQFP
144-Ball fpBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPLSI2192VE-135LB144 | 功能描述:CPLD - 复杂可编程逻辑器件 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI2192VE-135-LB144 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE135LB144I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE135LT128 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE-135LT128 | 功能描述:CPLD - 复杂可编程逻辑器件 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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