参数资料
型号: IXDD404SI-16
厂商: IXYS
文件页数: 10/12页
文件大小: 0K
描述: IC MOSFET DRVR LS 4A DUAL 16SOIC
产品变化通告: Discontinuation Notice 15/Jun/2010
标准包装: 47
配置: 低端
输入类型: 非反相
延迟时间: 36ns
电流 - 峰: 4A
配置数: 2
输出数: 2
电源电压: 4.5 V ~ 35 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
配用: EVDD404-ND - EVALUATION BOARD FOR IXDD404 DVR
IXDD404
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 26, can cause the current
through the module to flow in excess of 60A for 10 μ s or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
The IXDD404 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Thus, the IXDD404 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD404 is designed to not only provide ± 4A per output
under normal conditions, but also to allow it's outputs to go into
a high impedance state. This permits the IXDD404 output to
control a separate weak pull-down circuit during detected
overcurrent shutdown conditions to limit and separately con-
trol d VGS /dt gate turnoff. This circuit is shown in Figure 27.
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFD100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000-
series devices operate with a V CC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD404 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD408 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD404 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD404 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD404, preventing its destruction.
Figure 29 - Application Test Diagram
IXDD404
Ld
10uH
Rd
0.1ohm
+
-
VB
VCC
VCCA
Rg
High_Power
IN
EN
OUT
Rsh
1600ohm
1ohm
IXFN100N20
+
-
VCC
+
-
VIN
DGND
SUB
Rs
Low_Power
2N7002/PLP
One ShotCircuit
Rcomp
R+
10kohm
Ls
20nH
0
NOT1
CD4049A
Ros
1Mohm
Cos
1pF
NAND
CD4011A
NOT2
CD4049A
Q
R
5kohm
Ccomp
1pF
Comp
LM339
V+
V-
+
-
REF
+
-
C+
100pF
NOT3
CD4049A
NOR1
CD4001A
S
EN
NOR2
CD4001A
SR Flip-Flop
10
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