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参数资料
| 型号： | IXS839BQ2 |
| 厂商： | IXYS |
| 文件页数： | 11/11页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER SYNC BUCK 10QFN |
| 标准包装： | 121 |
| 配置： | 高端和低端，同步 |
| 输入类型： | 非反相 |
| 延迟时间： | 35ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 24V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFQFN 裸露焊盘 |
| 供应商设备封装： | 10-QFN |
| 包装： | 管件 |
Q GATE
? V BST
IXYS
waiting for the voltage on the High Side Gate
Driver Output pin to reach 1 volt, the overlap
protection circuit ensures that Q1 is OFF before Q2
turns on.
Similarly, when the PWM input transitions high, Q2
begins to turn OFF, and Q1 turns ON after the
overlap protection circuit detects that the voltage at
the Low-Side Gate Driver output has dropped
below 1 volt. Once the driver output voltage falls
below 1 volt, the overlap protection circuit initiates
a delay timer that adds additional delay set by the
external capacitor connected to the DLY pin. This
programmable delay circuit allows adjustments to
optimize performance based on the switching
characteristics of the external power MOSFET.
Low-Side Driver Shutdown
The IXS839A/B include a Low-Side Gate Driver
shutdown feature. A logic low signal at the LSD
input shuts down the Low Side Gate Driver, and in
turn the synchronous recti ? er FET. This signal can
be used to achieve maximum battery life under
light load conditions and maximum efficiency under
heavy load conditions. Under heavy load
conditions, LSD should be high so that the
synchronous switch is controlled by the PWM
signal for maximum efficiency. Under light load
conditions the LSD can be low to disable the Low
Side Gate Driver so the switching current can be
minimized.
Shutdown
For optimal system power management, the
IXS839A/B drivers can be shut down to conserve
power. When the SD pin is high, the IXS839A/B
are enabled for normal operation. Pulling the SD
pin low forces the HGD and LGD outputs low, and
reduces the supply current by disabling the internal
reference.
Under Voltage Lockout (IXS839 and IXS839B)
The Under Voltage Lockout (UVLO) circuit holds
both driver outputs low during VDD supply ramp-
up. The UVLO logic becomes active and in control
of the driver outputs at a supply voltage of no
greater than 1.5 V. When the supply voltage rises
above the UVLO upper threshold the circuit allows
the PWM input to control the drivers.
IXS839 / IXS839A / IXS839B
Application Information
Supply Capacitor Selection
A 1 uF ceramic bypass capacitor is recommended
for the VDD input to provide noise suppression.
The bypass capacitor should be located as close
as possible to the IXS939/A/B.
Bootstrap Circuit
The bootstrap circuit requires a charge storage
capacitor CBST and a Schottky diode DBST, as
shown in Figure 1. Selecting these components
should be done with consideration of the electrical
characteristics of the high-side FET chosen.
The bootstrap capacitor voltage rating must
exceed the maximum input voltage, (VIN) + the
maximum VDD voltage. The capacitance is
determined using the following equation:
C BST =
Where, QGATE is the total gate charge of Q1, and
? VBST is the allowable Q1 voltage droop.
To maximize the available drive for Q1 in the
bootstrap circuit a Schottky diode is recommended.
The bootstrap diode voltage rating must exceed
the maximum input voltage, (VIN) + the maximum
VDD voltage. The average forward current can be
estimated by:
I F(AVG) = Q GATE X F MAX
where F MAX is the maximum PWM input switching
frequency. Peak surge current is dependent on the
source impedance of the 5V supply and the ESR
of CBST, and should be checked in-circuit.
Delay Capacitor Selection
A ceramic capacitor is recommended for the DLY
input, and should be located as close a possible to
the DLY pin.
Printed Circuit Board Layout Considerations
Use the following general guidelines when
designing printed circuit boards:
1. Trace out the high current paths and use short,
wide traces to make these connections.
2. Locate the VDD bypass capacitor as close as
possible to the VDD and PGND pins.
3. Connect the source of the Lower MOSFET,
(Q2) as close as possible the PGND.
11
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相关代理商/技术参数 |
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| IXS839BQ2T/R | 功能描述:功率驱动器IC 2 / 4 Amps 30V 2.2 / 1.2 Ohm Rds RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| IXS839S1 | 功能描述:功率驱动器IC 2 / 4 Amps 30V 2.2 / 1.2 Ohm Rds RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| IXS839S1T/R | 功能描述:功率驱动器IC 2 / 4 Amps 30V 2.2 / 1.2 Ohm Rds RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| IXSA10N60B2D1 | 功能描述:IGBT 晶体管 10 Amps 600V 2.5 Rds RoHS:否 制造商:Fairchild Semiconductor 配置: 集电极—发射极最大电压 VCEO:650 V 集电极—射极饱和电压:2.3 V 栅极/发射极最大电压:20 V 在25 C的连续集电极电流:150 A 栅极—射极漏泄电流:400 nA 功率耗散:187 W 最大工作温度: 封装 / 箱体:TO-247 封装:Tube |
| IXSA12N60AU1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | IGBT | N-CHAN | 600V V(BR)CES | 24A I(C) | TO-263AA |
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