参数资料
| 型号： | KAD2708C-27Q68 |
| 厂商： | Intersil |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 275MSPS PAR 68-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 8 |
| 采样率（每秒）： | 275M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 294mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 供应商设备封装： | 68-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6812.1
April 14, 2011
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the inputs for the analog
input and clock signals. Locate transformers, drivers and
terminations as close to the chip as possible.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close to
device pins. Longer traces will increase inductance, resulting
in diminished dynamic performance and accuracy. Make
sure that connections to ground are direct and low
impedance.
LVCMOS Outputs
Output traces and connections must be designed for 50
Ω
characteristic impedance. Avoid crossing ground and
power-plane breaks with signal traces.
Unused Inputs
The RST and 2SC inputs are internally pulled up, and can be
left open-circuit if not used.
CLKDIV is internally pulled low, which divides the input clock
by two.
VREFSEL is internally pulled up. It must be held low for internal
reference, but can be left open for external reference.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02.
Integral Non-Linearity (INL) is the deviation of each individual
code from a line drawn from negative full-scale (1/2 LSB below
the first code transition) through positive full-scale (1/2 LSB
above the last code transition). The deviation of any given code
from this line is measured from the center of that code.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N - 1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight. Its value in terms of input voltage is VFS/2.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the corresponding data.
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in power supply voltage to the input voltage
necessary to negate the resultant change in output code.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (SNR) (without Harmonics) is the
ratio of the RMS signal amplitude to the RMS sum of all
other spectral components below one-half the sampling
frequency, excluding harmonics and DC.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the peak spurious
spectral component. The peak spurious spectral component
may or may not be a harmonic.
Two-Tone SFDR is the ratio of the RMS value of either input
tone to the RMS value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
KAD2708C
相关PDF资料 |
PDF描述 |
|---|---|
| KAD2708L-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2710C-27Q68 | IC ADC 10BIT 275MSPS PAR 68-QFN |
| KAD2710L-21Q68 | IC ADC 10BIT 210MSPS SGL 68-QFN |
| KAD5510P-25Q48 | IC ADC 10BIT CMOS 250MSPS 48QFN |
| KAD5510P-50Q72 | IC ADC 10BIT 500MSPS SGL 72-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD2708L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit, 350MSPS Analog-to-Digital Converter |
| KAD2708L_11 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:8-Bit, 350/275/210/170/105MSPS A/D Converter |
| KAD2708L-10Q68 | 功能描述:IC ADC 8BIT 105MSPS SGL 68-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| KAD2708L-17Q68 | 功能描述:IC ADC 8BIT 170MSPS SGL 68-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| KAD2708L-21Q68 | 功能描述:IC ADC 8BIT 210MSPS SGL 68-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。