参数资料
| 型号： | KAD2710L-21Q68 |
| 厂商： | Intersil |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 210MSPS SGL 68-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 210M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 268mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 供应商设备封装： | 68-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
13
FN6818.0
December 5, 2008
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance.
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier can be used in applications that
require dc coupling. In this configuration the amplifier will
typically determine the achievable SNR and distortion. A
typical differential amplifier circuit is shown in Figure 25.
Clock Input
The sample clock input circuit is a differential pair (see
Figure 29). Driving these inputs with a high level (up to
1.8VPP on each input) sine or square wave will provide the
lowest jitter performance.
The recommended drive circuit is shown in Figure 26. The
clock can be driven single-ended, but this will reduce the
edge rate and may impact SNR performance.
Use of the clock divider is optional. The KAD2710L's ADC
requires a clock with 50% duty cycle for optimum
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate and use the
KAD2710L's divide-by-2 setting. This frequency divider uses
the rising edge of the clock, so 50% clock duty cycle is
assured. Table 2 describes the CLKDIV connection.
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
is illustrated in Figure 27.
Where tJ is the RMS uncertainty in the sampling instant.
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
ADT1-1WT
0.1F
KAD2710L
VCM
50
O
0.01F
Analog
In
ADT1-1WT
Ω
FIGURE 24. TRANSFORMER INPUT FOR HIGH IF
APPLICATIONS
ADTL1-12
0.1F
KAD2710L
VCM
ADTL1-12
1000pF
Analog
Input
25
O
25
O
Ω
KAD2710
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Analog
Input
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
Ω
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
AVDD
1
TC4-1W
1nF
AVDD2
200O
CLKP
CLKN
1kO
1nF
Clock
Input
FIGURE 26. RECOMMENDED CLOCK DRIVE
Ω
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
tj=100p s
tj=10p s
tj=1ps
tj=0.1p s
10 Bits
12 Bits
14 Bits
50
55
60
65
70
75
80
85
90
95
100
1
10
100
1000
Input Frequency - MHz
SN
R-
d
B
FIGURE 27. SNR vs CLOCK JITTER
KAD2710L
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD2710L-27Q68 | 功能描述:IC ADC 10BIT 275MSPS SGL 68-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 位数:10 采样率（每秒）:357k 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 功率耗散（最大）:830µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:剪切带 (CT) 输入数目和类型:2 个单端，单极；2 个单端，双极；1 个差分，单极；1 个差分，双极 产品目录页面:1396 (CN2011-ZH PDF) 其它名称:MAX1395ETB+TCT |
| KA-D2E | 制造商:Leach International Corporation 功能描述:MID RANGE - Bulk |
| KA-D2F | 制造商:Leach International Corporation 功能描述:EM RLY 4PDT 10A 115VAC SCKT - Bulk |
| KA-D4E | 制造商:Leach International Corporation 功能描述:EM RLY 4PDT 10A 28VAC SCKT - Bulk |
| KA-D4F | 制造商:Leach International Corporation 功能描述:EM RLY 4PDT 10A 115VAC SCKT - Bulk |
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