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| 型号： | KITMMA955XLEVM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 18/26页 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION FOR MMA955XL |
| 标准包装： | 1 |
| 传感器类型： | 加速计，3 轴 |
| 传感范围： | ±2g，4g，8g |
| 接口： | I²C |
| 灵敏度： | 0.061mg/LSB，0.122mg/LSB，0.244mg/LSB |
| 嵌入式： | 否 |
| 已供物品： | 2 个板，线缆，文档 |
| 已用 IC / 零件： | MMA955XL |
4.11
AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 5 on page 15 . Unless otherwise specified, propagation delays are
measured from the 50-percent to 50-percent point. Rise and fall times are measured between the 10-percent and 90-percent
points, as shown in the following figure.
V IH
Low
High
Input Signal
Midpoint1
90%
50%
10%
Fall Time
V IL
Rise Time
Note: The midpoint is V IL + (V IH – V IL )/2.
Figure 7. Input signal measurement references
The subsequent figure shows the definitions of the following signal states:
? Active state, when a bus or signal is driven and enters a low-impedance state
? Three-stated, when a bus or signal is placed in a high-impedance state
? Data Valid state, when a signal level has reached V OL or V OH
? Data Invalid state, when a signal level is in transition between V OL and V OH
Data1 Valid
Data1
Data Invalid State
Data Active
Data1 Valid
Data2
Data
3-stated
Data3 Valid
Data3
Data Active
Figure 8. Signal states
4.12
General Timing Control
Table 11. General timing characteristics (1)
Characteristic
V DD rise time
POR release delay (2)
Warm-up time
Frequency of operation
System clock period
Full/Slow clock ratio
Oscillator frequency absolute accuracy @ 25°C
Oscillator frequency variation over temperature
(-40°C to 85°C vs. ambient)
Minimum RESET assertion duration
Symbol
T rvdd
T POR
T WU
F OPH
F OPL
t CYCH
t CYCL
—
—
—
t RA
Condition(s)
10% to 90%
Power-up
From STOP NC
Full Speed Clock
Slow Clock
Full Speed Clock
Slow Clock
—
Full Speed Clock
Slow Clock
—
Min
—
0.35
—
—
—
—
—
—
-5
-6
4T (3)
Typ
—
7
8
62.5
125
16
128
—
—
—
Max
1
1.5
—
—
—
—
—
—
+5
+6
—
Unit
ms
ms
sample
periods
MHz
KHz
ns
? s
%
%
—
1.
2.
3.
All conditions at nominal supply: V DD = V DDA = 1.8 V
This is the time measured from V DD = V POR until the internal reset signal is released.
In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 ? s.
MMA955xL
Sensors
18
Freescale Semiconductor, Inc.
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