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| 型号： | KITMMA955XLEVM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/26页 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION FOR MMA955XL |
| 标准包装： | 1 |
| 传感器类型： | 加速计，3 轴 |
| 传感范围： | ±2g，4g，8g |
| 接口： | I²C |
| 灵敏度： | 0.061mg/LSB，0.122mg/LSB，0.244mg/LSB |
| 嵌入式： | 否 |
| 已供物品： | 2 个板，线缆，文档 |
| 已用 IC / 零件： | MMA955XL |
4.13
I 2 C Timing
This device includes a slave I 2 C module that can be used to control the sensor and can be active 100 percent of the time. It also
includes a master/slave I 2 C module that should be used only during CPU run mode ( ? D ).
SDA
t f
t LOW
t r
t SU; DAT
t f
t HD; STA
t SP
t r
t BUF
SCL
S
t HD; STA
t HD; DAT
t HIGH
t SU; STA
SR
t SU; STO
P
S
Figure 9. I 2 C standard and fast-mode timing
4.13.1
Slave
I 2 C
Table 12. I 2 C Speed Ranges
Mode
Standard
Fast
Fast +
High-speed
supported
Max Baud
Rate (f SCL )
100 KHz
400 KHz
1 MHz
2.0 MHz
Min
Bit Time
10 ?? s
2.5 ?? s
1 ?? s
0.5 ? s
Min SCL Low
(t LOW )
4.7 ? s
1.3 ? s
500 ns
200 ns
Min SCL High
(t HIGH )
4 ? s
0.6 ? s
260 ns
200 ns
Min Data setup Time
(t SU; DAT )
250 ns
100 ns
50 ns
10 ns (2)
Min/Max Data Hold Time
(t HD; DAT )
0 ? s/3.45 ? s (1)
0 ? s/0.9 ? s (1)
0 ? s/0.45 ? s (1)
0 ns/70 ns (100 pf) (2)
1.
2.
The maximum t HD; DAT must be at least a transmission time less than t VD;DAT or t VD;ACK . For details, see the I 2 C standard.
Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual
(MMA955xLRM).
4.13.2
Master I 2 C Timing
The master I 2 C module should only be used when the system clock is running at full rate. Do not attempt to use the master I 2 C
module across frames in which a portion of the time is spent in low-speed mode.
Table 13. Master I 2 C timing
Characteristic
Symbol
Standard Mode
Min Max
Fast Mode
Min Max
Unit
SCL clock frequency
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time for I 2 C-bus devices
Data setup time
Setup time for STOP condition
Bus-free time between STOP and START condition
Pulse width of spikes that must be suppressed by the input filter
f SCL
t HD; STA
t LOW
t HIGH
t SU; STA
t HD; DAT
t SU; DAT
t SU; STO
t BUF
t SP
0
4.0
4.7
4.0
4.7
0 (1)
250 (3)
4.0
4.7
N/A
100
—
—
—
—
3.45 (2)
—
—
—
N/A
0
0.6
1.3
0.6
0.6
0 (1)
100 (3) (4)
0.6
1.3
0
400
—
—
—
—
0.9 (2)
—
—
—
50
kHz
? s
? s
? s
? s
? s
ns
μs
μs
ns
1.
2.
3.
4.
The master mode I 2 C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-
ative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum t HD; DAT must be met only if the device does not stretch the LOW period (t LOW ) of the SCL signal.
Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
A fast-mode I 2 C bus device can be used in a Standard mode I 2 C bus system, but the requirement t SU; DAT ? 250 ns must then be met. This will automat-
ically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t SU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I 2 C bus specification) before the SCL
line is released.
MMA955xL
Sensors
Freescale Semiconductor, Inc.
19
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