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| 型号： | KMC8113TMP4800V |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 11/44页 |
| 文件大小： | 0K |
| 描述： | IC DSP 300/400MHZ 431FCPGA |
| 标准包装： | 2 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | 以太网，I²C，TDM，UART |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.10V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 431-BFBGA，FCBGA |
| 供应商设备封装： | 431-FCPBGA（20x20） |
| 包装： | 托盘 |
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Electrical Characteristics
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
19
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
2.5.4.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
VDD and VDDH are both at their nominal levels.
Table 10. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8113 and configures various attributes of the
MSC8113. On PORESET, the entire MSC8113 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8113. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8113 Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8113 detects an external assertion of SRESET only if it occurs
while the MSC8113 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
Software
watchdog reset
Internal
When the MSC8113 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor reset
Internal
When the MSC8113 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
Host reset
command through
the TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Table 11. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On
Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog or
Bus Monitor)
External
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
Yes
NoNoNo
SPLL state reset
Yes
No
System reset configuration write through
the DSI
Yes
NoNoNo
System reset configuration write though
the system bus
Yes
No
HRESET driven
Yes
No
SIU registers reset
Yes
No
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
Yes
SRESET driven
Yes
Depends on command
SC140 extended cores reset
Yes
MQBS reset
Yes
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