参数资料
型号: KMPC8313EZQAFFB
厂商: Freescale Semiconductor
文件页数: 21/99页
文件大小: 0K
描述: IC MPU POWERQUICC II 516-PBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
封装/外壳: 516-BBGA 裸露焊盘
供应商设备封装: 516-PBGAPGE(27x27)
包装: 托盘
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
28
Freescale Semiconductor
This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes interface of
MPC8313E as shown in Figure 15, where CTX is the external (on board) AC-coupled capacitor. Each
output pin of the SerDes transmitter differential pair features a 50-
output impedance. Each input of the
SerDes receiver differential pair features 50-
on-die termination to XCOREVSS. The reference circuit
of the SerDes transmitter and receiver is shown in Figure 33.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in Section 22.5, “Connection Recommendations,” as long as such termination does not violate
the desired POR configuration requirement on these pins, if applicable.
When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead, the
SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins.
8.3.1
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 9,
GTX_CLK
tRGT
tRGTH
tSKRGT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
tSKRGT
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